A:
tapping is done to avoid latch up effect......hope u know latch up effect...
so for that n tap is connected to p transistor....by connecting p tap over VDD
similarly for p tap ....is connected to n transistor....connected to VSS...

B:
well tap cells are used to limit resistance between power or ground connections to wells of the substrate. taps are traditionally used so that your VDD and GND are connected to subtrate and n-wells respectively. This is to help tie them to your VDD and GND levels so that they don't drift too much (especially towards the middle of the chip) and cause latchup.
The rules for welltaps and endcaps are very technology dependent. Some technologies don't require them at all (or, the taps are built in to the std cells), and for other technologies you may need a welltap every X microns, and endcaps at the end of every std cell row. The DRC deck should flag any issues regarding welltaps/endcaps, which is one good reason to run an early DRC. You will have to consult the design rule manual for your process.

C:
Std cell doesn't contains these TAP connections. Actually you don't need to use TAP connection in all the cells. It will increase the cell area & as well as chip area. Normally we place a TAP cell for around 5 or more std cells combined while doing top level routing

Qoute from dc user guid: Examples of physical-only cells include filler cells, tap cells, flip-chip pad cells, endcap cells, and decap cells. Although physical-only cells have no logic function, they create placement blockages that the tool considers during optimization and congestion analysis.