只写成 `include "define_file.v" 是不行的,要使用绝对路径,如`include "F:/110503_Test/rtl/define_file.v"。 详情如下: QUESTION: From Xilinx ISE I get the following error: ERROR:HDLCompilers:26 - "rtl/definitions.v" line 2 expecting 'EOF', found 'parameter' When I compile in ModelSim ...