| |
//异步复位,同步解复位
module rst_ctrl
(
input clk,
input rst,
input data_in,
output reg data_out
);
//****************************************
//proc rst, Asynchronous Assertion, Synchronous Deassertion
reg rst_dly1;
reg rst_dly2;
reg rst_prc;
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1)
begin
rst_dly1 <= 1'b1;
rst_dly2 <= 1'b1;
end
else
begin
rst_dly1 <= 1'b0;
rst_dly2 <= rst_dly1;
end
end
always @ (posedge clk or posedge rst)
begin
if (rst == 1'b1)
rst_prc <= 1'b1;
else
rst_prc <= rst_dly2;
end
//****************************************
always @ (posedge clk or posedge rst_prc)
begin
if (rst_prc == 1'b1)
data_out <= 1'b0;
else
data_out <= data_in;
end
endmodule