下面的例子是一个16选1的多路选择器代码1给出的是直接选择的方式；代码2给出了多一级流水线的代码时序的方式。代码2相比代码1资源会多一些，但时序方面的性能会更好。

module mux16t1_a
    (
    input                   rst,
    input                   clk,

    input           [3:0]   sel,
    input           [7:0]   datain0,
    input           [7:0]   datain1,
    input           [7:0]   datain2,
    input           [7:0]   datain3,
    input           [7:0]   datain4,
    input           [7:0]   datain5,
    input           [7:0]   datain6,
    input           [7:0]   datain7,
    input           [7:0]   datain8,
    input           [7:0]   datain9,
    input           [7:0]   datain10,
    input           [7:0]   datain11,
    input           [7:0]   datain12,
    input           [7:0]   datain13,
    input           [7:0]   datain14,
    input           [7:0]   datain15,

    output  reg     [7:0]   dataout

    );

always @ (posedge clk or posedge rst)
begin
    if (rst == 1'b1)
        dataout <= 8'd0;
    else
    begin
        case (sel)
            4'd0: dataout <= datain0;
            4'd1: dataout <= datain1;
            4'd2: dataout <= datain2;
            4'd3: dataout <= datain3;
            4'd4: dataout <= datain4;
            4'd5: dataout <= datain5;
            4'd6: dataout <= datain6;
            4'd7: dataout <= datain7;
            4'd8: dataout <= datain8;
            4'd9: dataout <= datain9;
            4'd10: dataout <= datain10;
            4'd11: dataout <= datain11;
            4'd12: dataout <= datain12;
            4'd13: dataout <= datain13;
            4'd14: dataout <= datain14;
            4'd15: dataout <= datain15;
            default: dataout <= datain0;
        endcase
    end
end

endmodule

///////////////////////////////////////////////////////////////////////////////////////////////

module mux16t1_b
    (
    input                   rst,
    input                   clk,

    input           [3:0]   sel,
    input           [7:0]   datain0,
    input           [7:0]   datain1,
    input           [7:0]   datain2,
    input           [7:0]   datain3,
    input           [7:0]   datain4,
    input           [7:0]   datain5,
    input           [7:0]   datain6,
    input           [7:0]   datain7,
    input           [7:0]   datain8,
    input           [7:0]   datain9,
    input           [7:0]   datain10,
    input           [7:0]   datain11,
    input           [7:0]   datain12,
    input           [7:0]   datain13,
    input           [7:0]   datain14,
    input           [7:0]   datain15,

    output  reg     [7:0]   dataout

    );

reg     [7:0]   dataout_pre0;
reg     [7:0]   dataout_pre1;
reg     [7:0]   dataout_pre2;
reg     [7:0]   dataout_pre3;

always @ (posedge clk or posedge rst)
begin
    if (rst == 1'b1)
        dataout_pre0 <= 8'd0;
    else
    begin
        case (sel[1:0])
            2'd0: dataout_pre0 <= datain0;
            2'd1: dataout_pre0 <= datain1;
            2'd2: dataout_pre0 <= datain2;
            2'd3: dataout_pre0 <= datain3;
            default: dataout_pre0 <= datain0;
        endcase
    end
end

always @ (posedge clk or posedge rst)
begin
    if (rst == 1'b1)
        dataout_pre1 <= 8'd0;
    else
    begin
        case (sel[1:0])
            2'd0: dataout_pre1 <= datain4;
            2'd1: dataout_pre1 <= datain5;
            2'd2: dataout_pre1 <= datain6;
            2'd3: dataout_pre1 <= datain7;
            default: dataout_pre1 <= datain4;
        endcase
    end
end

always @ (posedge clk or posedge rst)
begin
    if (rst == 1'b1)
        dataout_pre2 <= 8'd0;
    else
    begin
        case (sel[1:0])
            2'd0: dataout_pre2 <= datain8;
            2'd1: dataout_pre2 <= datain9;
            2'd2: dataout_pre2 <= datain10;
            2'd3: dataout_pre2 <= datain11;
            default: dataout_pre2 <= datain8;
        endcase
    end
end

always @ (posedge clk or posedge rst)
begin
    if (rst == 1'b1)
        dataout_pre3 <= 8'd0;
    else
    begin
        case (sel[1:0])
            2'd0: dataout_pre3 <= datain12;
            2'd1: dataout_pre3 <= datain13;
            2'd2: dataout_pre3 <= datain14;
            2'd3: dataout_pre3 <= datain15;
            default: dataout_pre3 <= datain12;
        endcase
    end
end

always @ (posedge clk or posedge rst)
begin
    if (rst == 1'b1)
        dataout <= 8'd0;
    else
    begin
        case (sel[3:2])
            2'd0: dataout <= dataout_pre0;
            2'd1: dataout <= dataout_pre1;
            2'd2: dataout <= dataout_pre2;
            2'd3: dataout <= dataout_pre3;
            default: dataout <= dataout_pre0;
        endcase
    end
end

endmodule