`timescale 1ns/1ns
module edge_det#
    (
    parameter EDGE_DETECT="POSEDGE"
    )
    (
    input   clk,
    input   rst,
    input   signal_in,

    output  signal_edge
    );

generate
    if (EDGE_DETECT == "POSEDGE")
    begin: POSE_EDGE
        reg     signal_in_dly1;
        reg     signal_in_dly2;
        reg     signal_in_dly3;
        reg     signal_rise;

        always @ (posedge clk or posedge rst)
        begin
            if (rst == 1'b1)
            begin
                signal_in_dly1 <= 1'b0;
                signal_in_dly2 <= 1'b0;
                signal_in_dly3 <= 1'b0;
            end
            else
            begin
                signal_in_dly1 <= signal_in;
                signal_in_dly2 <= signal_in_dly1;
                signal_in_dly3 <= signal_in_dly2;
            end
        end

        always @ (posedge clk or posedge rst)
        begin
            if (rst == 1'b1)
                signal_rise <= 1'b0;
            else
                signal_rise <= ~signal_in_dly3 && signal_in_dly2;
        end

        assign signal_edge = signal_rise;

    end
    else if (EDGE_DETECT == "NEGEDGE")
    begin: NEGE_EDGE
        reg     signal_in_dly1;
        reg     signal_in_dly2;
        reg     signal_in_dly3;
        reg     signal_fall;

        always @ (posedge clk or posedge rst)
        begin
            if (rst == 1'b1)
            begin
                signal_in_dly1 <= 1'b0;
                signal_in_dly2 <= 1'b0;
                signal_in_dly3 <= 1'b0;
            end
            else
            begin
                signal_in_dly1 <= signal_in;
                signal_in_dly2 <= signal_in_dly1;
                signal_in_dly3 <= signal_in_dly2;
            end
        end

        always @ (posedge clk or negedge rst)
        begin
            if (rst == 1'b0)
                signal_fall <= 1'b0;
            else
                signal_fall <= signal_in_dly3 && (~signal_in_dly2);
        end

        assign signal_edge = signal_fall;
    end
    else if (EDGE_DETECT == "DUALDGE")
    begin: DUAL_EDGE
        reg     signal_in_dly1;
        reg     signal_in_dly2;
        reg     signal_in_dly3;
        reg     signal_rise_fall;

        always @ (posedge clk or posedge rst)
        begin
            if (rst == 1'b1)
            begin
                signal_in_dly1 <= 1'b0;
                signal_in_dly2 <= 1'b0;
                signal_in_dly3 <= 1'b0;
            end
            else
            begin
                signal_in_dly1 <= signal_in;
                signal_in_dly2 <= signal_in_dly1;
                signal_in_dly3 <= signal_in_dly2;
            end
        end

        always @ (posedge clk or posedge rst)
        begin
            if (rst == 1'b1)
                signal_rise_fall <= 1'b0;
            else
                signal_rise_fall <= signal_in_dly3 ^ signal_in_dly2;
        end

        assign signal_edge = signal_rise_fall;
    end

endgenerate

endmodule