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Verlig小程序-verilog呼吸灯代码
| ||
module breathing_lamp(
input wire sclk,
input wire rst_n,
output reg [7:0] dout
);
parameter CHEN=50000-1;
reg [15:0] cnt;
reg [15:0] on_temp;
reg temp_flag;
wire wire_temp_flag;
reg led_direction;
reg[11:0] temp;
//counter of the 1000divider cnt=0~49999
always @(posedge sclk or negedge rst_n)
if(rst_n==1'd0)
begin
cnt<=16'd0;
temp_flag<=1'd0;
end
else if (cnt==CHEN)
begin
cnt<=16'd0;
temp_flag<=1'b1;
end
else
begin
cnt<=cnt+16'd1;
temp_flag<=1'b0;
end
assign wire_temp_flag=temp_flag;
always @(posedge wire_temp_flag or negedge rst_n)
if(rst_n==1'd0)
begin
led_direction<=1'd0;
temp<=16'd0;
end
else if (led_direction==1'd0)
begin
temp<=temp+16'd1;
if (temp==12'd1000)
led_direction<=1'd1;
end
else if (led_direction==1'd1)
begin
temp<=temp-16'd1;
if (temp==12'd0)
led_direction<=1'd0;
end
always @(posedge wire_temp_flag or negedge rst_n)
if(rst_n==1'd0)
on_temp<=16'd0;
else if (led_direction==1'd0)
on_temp=on_temp+16'd50;
else if (led_direction==1'd1)
on_temp=on_temp-16'd50;
always @(posedge sclk or negedge rst_n)
if(rst_n==1'd0)
dout<=8'd0;
else if (cnt<on_temp)
dout<=8'b1111_1111;
else dout<=8'd0;
endmodule
/1 
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