发现设计芯片的应用跟低功耗很有关系，平时就知道一个降低电压来降低功耗，还是要系统学习一下。

芯片设计进阶之路——低功耗深入理解（一）

https://zhuanlan.zhihu.com/p/137937714

芯片设计中的功耗挑战和低功耗设计

https://zhuanlan.zhihu.com/p/640092988

2023_11_07 二

The key techniques to reach state-of-the-art energy efficiency are: 1) ultra-low-voltage (ULV) operation enabled by body biasing; 2) pulse-based communication for high duty cycling; and 3) massively low-frequency operated architecture to reduce dynamic power consumption.

The relationship between frequency and power consumption in electronic devices, particularly in digital circuits, is a critical

 consideration in modern integrated circuit design. Generally, the power consumption of a digital circuit 

is directly proportional to its operating frequency. The key factors influencing this relationship include:

1. **Switching Activity**: As the operating frequency increases, the number of transitions or switching activities within the 

circuit increases, leading to a rise in dynamic power consumption. This is because the power dissipated during each transition

 contributes to the overall power consumption of the circuit.

2. **Short-Circuit Power**: At higher frequencies, the time available for a gate to transition from one state to another decreases,

 resulting in a higher possibility of short-circuit current flowing during the switching process. This contributes to an increase in

 power consumption.

3. **Leakage Currents**: While not directly related to frequency, higher temperatures associated with increased frequency can

 lead to higher leakage currents, which add to the overall power consumption of the circuit.

4. **Supply Voltage**: In some cases, to achieve higher frequencies, it might be necessary to increase the supply voltage. 

This increase in supply voltage leads to a quadratic increase in power consumption.

5. **Clock Distribution Network**: The power consumed by the clock distribution network is also proportional to the clock

 frequency, especially in high-performance systems where clock distribution consumes a significant portion of the overall power.

Designers often have to strike a balance between performance and power consumption, as increasing the operating 

frequency generally results in higher power consumption, which can lead to issues with heat dissipation, battery life in

 portable devices, and overall system reliability. Various power-saving techniques are employed, such as dynamic voltage 

and frequency scaling (DVFS), clock gating, and power gating, to manage power consumption while maintaining acceptable 

performance levels.

2023_12_16 六

低功耗技术之Agressive duty cycle。

激进的占空比技术自然说的是导通时间越来越小，电路工作在关闭状态的时间越长，能耗当然越低。

这个占空比是要考虑总时间长度的，不是可以scale down的。比如说0.01% per hour，那就是一小时内有0.36s可以工作。这就够了，不能scale down。如果你采用OOK调制，OOK的数据率在0.36s里该设置多少就是多少。比如1MHz，那在1us的周期内OOK信号导通时间是多少呢，也就是占空比是多少。这时候就不是0.01%了，只要你能在0.36s里把数据传完（这跟数据率有关，1MHz, 0.36可以传360 kbit），占空比设置多少可以随意。

当然，理论上随意，实际上越小功耗也就越小，但要电路正常工作，又不可能无限小，比如考虑输出功率、PLL的锁定时间、VCO起振时间等等。