library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity jingtai is
     port(clk   :in std_logic;
         seg1   :out std_logic_vector(7 downto 0);
         seg_dat:out std_logic_vector(7 downto 0));
end jingtai;

architecture one of jingtai is
    signal cnt8   :std_logic_vector(2 downto 0);
    signal clk_tem:std_logic;
    signal cnt    :std_logic_vector(25 downto 0);
begin
      
process(clk)
begin
  if clk'event and clk='1' then
      if cnt=600  then
         clk_tem<=not clk_tem;--取反，分频
         cnt<=(others=>'0');
      else
         cnt<=cnt+1;
      end if;
  end if;
end process;

 p1:process(clk_tem)
    begin
       if(clk_tem'event and clk_tem='1') then
          if(cnt8="111")then
             cnt8<="000";
          else
             cnt8<=cnt8+1;
          end if;
       end if;
     end process p1;

p2:process(clk_tem)
       begin
       case cnt8 is
          when"000"=>seg_dat<="01111111";
          when"001"=>seg_dat<="10111111";
          when"010"=>seg_dat<="11011111";
          when"011"=>seg_dat<="11101111";
          when"100"=>seg_dat<="11110111";
          when"101"=>seg_dat<="11111011";
          when"110"=>seg_dat<="11111101";
          when"111"=>seg_dat<="11111110";
          when thers=>null;
       end case;
       end process p2;

p3:process(clk_tem)
   begin
       case cnt8 is
          when"000"=>seg1<="01111001";  --1
          when"001"=>seg1<="00100100";  --2
          when"010"=>seg1<="00110000";  --3
          when"011"=>seg1<="00011001";  --4
          when"100"=>seg1<="00010010";  --5
          when"101"=>seg1<="00000010";  --6
          when"110"=>seg1<="01111000";  --7
          when"111"=>seg1<="00000000";  --8
          when thers=>null;
       end case;
   end process p3;
end one;