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The statements in this 'always' block are outside the scope 解决办法
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The statements in this 'always' block are outside the
scope of the synthesis policy的解决办法
我源代码如下，特别是红色显示部分。红色显示部分就是错误的原因。
always @(posedge CLK or negedge RESET)
begin
if (~RESET)
begin
wrtaddr_para <= 3'b0;
rdaddr_para <= 3'b0;
para0 <= 84'h00;
para1 <= 84'h00;
para2 <= 84'h00;
para3 <= 84'h00;
para_empty <= 1'b1;
end
else
begin
if (wrtsent_ready & (~para_empty))
begin
rdaddr_para <= rdaddr_para + 1;
case (rdaddr_para[1:0])
2'b01: wrtsent_para <= para1;
2'b10: wrtsent_para <= para2;
2'b11: wrtsent_para <= para3;
default: wrtsent_para <= para0;
endcase
end
end
if (wrtaddr_para == rdaddr_para)
para_empty <= 1'b1;
else
para_empty <= 1'b0;
end
修改后的代码如下：把这部分代码放到整个if...else的begin...end模块中。
always @(posedge CLK or negedge RESET)
begin
if (~RESET)
begin
wrtaddr_para <= 3'b0;
rdaddr_para <= 3'b0;
para0 <= 84'h00;
para1 <= 84'h00;
para2 <= 84'h00;
para3 <= 84'h00;
para_empty <= 1'b1;
end
else
begin
if (wrtsent_ready & (~para_empty))
begin
rdaddr_para <= rdaddr_para + 1;
case (rdaddr_para[1:0])
2'b01: wrtsent_para <= para1;
2'b10: wrtsent_para <= para2;
2'b11: wrtsent_para <= para3;
default: wrtsent_para <= para0;
endcase
end
if (wrtaddr_para == rdaddr_para)
para_empty <= 1'b1;
else
para_empty <= 1'b0;
end
end
源代码很长，我是为了说明问题，随意截取了一部分代码。如果直接把他粘贴走去验证这个错误，恐怕要失望了。
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