日志

JSSC201506

已有 945 次阅读| 2015-7-2 13:21 |个人分类:JSSC-ADC

A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques

Miki, T.; Morie, T.; Matsukawa, K.; Bando, Y.; Okumoto, T.; Obata, K.; Sakiyama, S.; Dosho, S.

Solid-State Circuits, IEEE Journal of

Year: 2015, Volume: 50, Issue: 6

Pages: 1372 - 1381, DOI: 10.1109/JSSC.2015.2417803

Highlight:

Firstly, the ADC repeats comparison of LSB by using redundant DAC to average comparator noise and improve SNR. The technique also corrects settling error adaptively, which extends operation speed to 50 MHz even though extra comparison period is added for averaging. Secondly, simple filtering method for reducing DAC noise is introduced to achieve further improvement of SNR. Finally, new dithering method is proposed to enhance SFDR. Injecting noise-shaped, multi-valued and uniform-distributed dither to input of the ADC, spurs caused by capacitance mismatches of DAC can be suppressed more effectively compared with conventional dithering.

A 0.003 mm ^{2} 10 b 240 MS/s 0.7 mW SAR ADC in 28 nm CMOS With Digital Error Correction and Correlated-Reversed Switching

Jen-Huan Tsai; Hui-Huan Wang; Yang-Chi Yen; Chang-Ming Lai; Yen-Ju Chen; Po-Chuin Huang; Ping-Hsuan Hsieh; Hsin Chen; Chao-Cheng Lee

Solid-State Circuits, IEEE Journal of

Year: 2015, Volume: 50, Issue: 6

Pages: 1382 - 1398, DOI: 10.1109/JSSC.2015.2413850

An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers

Lin, J.; Paik, D.; Seungjong Lee; Miyahara, M.; Matsuzawa, A.

Solid-State Circuits, IEEE Journal of

Year: 2015, Volume: 50, Issue: 6

Pages: 1399 - 1411, DOI: 10.1109/JSSC.2015.2415472

Highlight:

In this ADC, high-speed open-loop dynamic amplifiers with a common-mode detection technique are used as residue amplifiers to increase the ADC's speed, to enhance the robustness against supply voltage scaling, and to realize clockscalable power consumption. To mitigate the absolute gain constraint of the residue amplifiers in a pipeline ADC, the interpolated pipeline architecture is employed to shift the gain requirement from absolute to relative accuracy. To show the new requirements of the residue amplifiers, the effects of gain mismatch and nonlinearity of the dynamic amplifiers are analyzed.

A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging

Jiayoon Zhiyu Ru; Palattella, C.; Geraedts, P.; Klumperink, E.; Nauta, B.

Solid-State Circuits, IEEE Journal of

Year: 2015, Volume: 50, Issue: 6

Pages: 1412 - 1423, DOI: 10.1109/JSSC.2015.2414421