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Mixed Language Boundary and Mapping Rules

已有 787 次阅读| 2013-5-19 10:44

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Mixed Language Boundary and Mapping Rules

Note The following information is intended for advanced users.

General

The following restrictions apply to the boundaries between Vhdl and verilog design units/modules.

The boundary between VHDL and Verilog is enforced at design unit level.
A VHDL design is allowed to instantiate one or more Verilog modules.
Instantiation of a Verilog UDP inside a VHDL design is not supported.
A Verilog design can instantiate a VHDL component corresponding to a VHDL entity only. Instantiation of a VHDL configuration in a Verilog design is not supported.

Port Mapping

The following rules and limitations for port mapping are used in mixed language projects.

Supported VHDL port types:
- IN
- OUT
- INOUT
Note Buffer and linkage ports of VHDL are not supported.
Supported Verilog port types:
- INPUT
- OUTPUT
- INOUT
Note Connection to bi-directional pass switches in Verilog are not supported.
Unnamed Verilog ports are not allowed on mixed design boundary.
The following table shows supported VHDL and Verilog data types for ports on the mixed language design boundary:

VHDL Port	Verilog Port
bit	net
std_ulogic	net
std_logic	net
bit_vector	vector net
std_ulogic_vector	vector net
std_logic_vector	vector net

Note Verilog output port of type reg is supported on the mixed language boundary. On the boundary, an output reg port is treated as if it were an output net (wire) port.

Note Any other type found on mixed language boundary is considered an error.

Generics (Parameters) Mapping

Following VHDL generic types (and their Verilog equivalents) are supported.