//左边为原始内容，后边为函数执行后内容。
//--------------------------------------------------------functions
//列 递增修改 ，
ColInc(StartNum,LoopNum,StepNum,SkipLineNum,LoopNum) ColInc.vim
example:
ColInc(1)
abc abc01
ColInc(1,3) //把光标看在第一行的c后面，执行
abc abc01
abc abc02
abc abc03
ColInc(1,5,2) //以2递增
abc abc01
abc abc03
abc abc05
ColInc(1,5,1,2) //跳行递增，
abc abc01
abc abc
abc abc02
abc abc
abc abc03
abc abc
abc abc04
abc abc
abc abc05
SkipDel(SumNum,SkipLine,LoopNum) //跳行删除单词 ColInc.vim
example:
SkipDel(3,2)
abc
abc abc
abc
abc abc
abc
abc abc
abc
abc abc
example:
SkipDel(3,2) //
axx ss axx
bxx ss bxx
cxx ss cxx
dxx ss dxx
axx ss axx
bxx ss bxx
cxx ss cxx
dxx ss dxx
axx ss axx
bxx ss bxx
cxx ss cxx
dxx ss dxx
axx ss axx
bxx ss bxx
cxx ss cxx
dxx ss dxx
SkipInsert(SumNum,SkipLine,LoopNum) ColInc.vim
example:
SkipInsert(3,2,"ss") //跳行 插入
abc dd abc sss dd
abc dd abc dd
abc dd abc sss dd
abc dd abc dd
CreatWireReg(MaxBit,typeString,LoopNum) //自动生成wire或reg的定义 CreatWireReg.vim
set: please write .v file; insert falg(//endwire //endreg)
example:
CreatWireReg()
wire [ 7:0 ] abc ;
//endwire //endwire
abc = 8'h00; abc = 8'h00;
CreatWireReg()
reg [ 7:0 ] abc ;
//endreg //endreg
abc <= 8'h00; abc <= 8'h00;
CreatWireReg(8)
wire [ 7:0 ] abc ;
//endwire //endwire
abc = s1_1; abc = s1_1;
CreatWireReg(8)
reg [ 7:0 ] abc ;
//endwire //endwire
abc <= s1_1; abc <= s1_1;
CreatWireReg(8,"reg",4)
reg [ 7:0 ] abc00 ;
reg [ 7:0 ] abc01 ;
reg [ 7:0 ] abc02 ;
reg [ 7:0 ] abc03 ;
//endwire //endwire
abc00 <= s1_1; abc <= s1_1;
abc01 <= s1_1; abc <= s1_1;
abc02 <= s1_1; abc <= s1_1;
abc03 <= s1_1; abc <= s1_1;
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