Two factors to impact the reliability of chips, NBIT and HCI

NBIT (negative bias temperature instability), caused by the negative biasing in PMOS which generates trap on the interface between oxide and diffusion. It makes Vth increase and transconduction decrease. The decrease of Vth is could be 20mV (more than 20%). Some of the phenomenon could be recovery and some can’t (cause Vth shift). It usually occurs when the input of inverter is “0”, so changing the input could recover the NBIT.

HCI (hot carrier injection), as the IC technology scaling down, the power supply voltage doesn’t decrease so much because of noise, delay and non-linear scaling down threshold voltage. So the electrical field becomes large which is helpful for high velocity. However, the hot carrier becomes more apparent. The carrier acquired high energy will go through the barrier and into the oxide or subtract. Both of the carrier who got into oxide and the carrier which generates the trap in the interface will change the Vth, make threshold voltage shift.