代码：
  genvar ii;
  generate
    for (ii = 0; ii < 512; ii = ii + 1) begin : instruction_gen
      initial begin    //这段逻辑不能综合的原因是将逻辑放在了initial块中！
      // Load SWRITEs
        if(ii < NUM_SWRITES) begin
          instruction[ii] = swrite_instruction[(ii+1)*64-1:ii*64];
        // Load NWRITE_Rs
        end else if(ii < (NUM_SWRITES + NUM_NWRITERS)) begin
          instruction[ii] = nwriter_instruction[(ii-NUM_SWRITES+1)*64-1:(ii-NUM_SWRITES)*64];
        // Load NWRITEs
        end else if(ii < (NUM_SWRITES + NUM_NWRITERS + NUM_NWRITES)) begin
          instruction[ii] = nwrite_instruction[(ii-NUM_SWRITES-NUM_NWRITERS+1)*64-1:(ii-NUM_SWRITES-NUM_NWRITERS)*64];
        // Load NREADs
        end else if(ii < (NUM_SWRITES + NUM_NWRITERS + NUM_NWRITES + NUM_NREADS)) begin
          instruction[ii] = nread_instruction[(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES+1)*64-1:(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES)*64];
        // Load DBs
        end else if(ii < (NUM_SWRITES + NUM_NWRITERS + NUM_NWRITES + NUM_NREADS + NUM_DBS)) begin
          instruction[ii] = db_instruction[(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES-NUM_NREADS+1)*64-1:(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES-NUM_NREADS)*64];
        // Load MSGs
        end else if(ii < (NUM_SWRITES + NUM_NWRITERS + NUM_NWRITES + NUM_NREADS + NUM_DBS + NUM_MSGS)) begin
          instruction[ii] = msg_instruction[(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES-NUM_NREADS-NUM_DBS+1)*64-1:(ii-NUM_SWRITES-NUM_NWRITERS-NUM_NWRITES-NUM_NREADS-NUM_DBS)*64];
        end else begin
          instruction[ii] = 64'h0;
        end
      end
    end
  endgenerate
//////////////////////////////////////
      根据verilog-2001语法，for循环是可以被综合的，具体用在组合逻辑中的代码展开。比如对同一个信号或者模块连续赋值，或者例化多个重复性模块。
      但是，上述代码是不可以被综合的。
      仔细观察，这段代码主要逻辑放在了initial块中，本身就不可综合，其次，即使把initial块去除，也无法综合，因为for中存在判断逻辑。所以这段逻辑主要用在仿真中。
     真实设计中，尽量不要用for。