日志
latch 与 dff 电路上的区别
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dff:
module d_ff (
input clk,
input rst_n,
input en,
input d,
output reg q
);
input clk,
input rst_n,
input en,
input d,
output reg q
);
always @ (posedge clk or negedge rst_n)
if (!rst_n)
q <= 0;
else if (en)
q <= d;
endmodule
if (!rst_n)
q <= 0;
else if (en)
q <= d;
endmodule
latch:
module lat(Q, Q‘, D, clk, rst_n); // level-triggered latch behavioral model
input D,clk,rst_n;
output Q, Q';
reg Q;
input D,clk,rst_n;
output Q, Q';
reg Q;
always @(clk or rst_n or D)
begin
if(!rst_n)
Q=1'b0;
else if(clk)
else if(clk)
Q=D;
end
end
assign Q' = ~Q;
endmodule
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