| |
sd_banks | ra_addr | ca_addr | tck | tccd_cnt | trtp_cnt | twtr_len | tmod_len |
txsdll_len | trp_len | tmrd_len | trc_len | trfc_len | trefi | trrd_len | trcd_len |
tras_min | tras_max | tras_len | tfaw_len | twr_len | tzqcs_len | mem_speed | tdllk |
tmprr | twlo | twlmrd | txpr | tzqinit | tzqcl_len | tzqoper | tckesr |
tcksre | tcksrx |
由于synopsys DDR2 VIP v2016.06好像还有些问题,write_recovery以及cas_latency不是按jedec spec全随机。
(trtw_cnt计算有点问题,DDR2的twl应该直接是trl-1,而不是tal+tcwl)
SDCTRL的性能其实是验证中非常重要的部分,如果仅是功能对了,但DDR的bandwidth损失太大,那么其实设计也是失败了,存储的性能直接关系到了芯片的成败。从以往的经验来讲,DDR data rate利用率至少要能达到90%,才算是一个不错的设计。
SDCTRL性能最直观的数据是DDR port上的bandwidth利用率,但是光靠bandwidth统计并不能说明问题,验证必须要找到SDCTRL在哪些地方损失了性能,比如这些AC timing有没有达到最小值且被有效的隐藏。比如为了隐藏RCD,最常用的做法是切AB bank,就是在输入端连续的地址,被mapping到ddr的不同bank。
这是一个非常艰难的统计,但值得注意的一点就是,我们至少可以统计这些AC timing达到最小有效值的概率,从大方向上找到性能的损失。
以下简单列出比较关心的AC timing(都换算为DDR clock cycle)
tCCD | CAS to CAS delay >= tCCD |
tRTP | READ to PRE delay for each bank; READ to PREA >= AL+BL/2+ max(tRTP,2) -2 |
tRTW | READ to WRITE delay >= tRTW |
tWTR | WRITE to READ delay >= tWL-tAL+BL/2 + tWRT |
tRP | PRE to ACT delay for each bank;PREA to other cmd delay >= tRP |
tRC | ACT to ACT delay for each bank >= tRC |
tRRD | ACT to ACT delay regardless of bank number >=tRRD |
tRFC | REF to any valid cmd delay>=tRFC |
tRCD | ACT to WRITE or READ delay for each bank>= tRCD+tAL |
tRAS | ACT to PRE delay for each bank; ACT to PREA delay >= tRAS |
tFAW | no more than 4 ACT in a rolling tFAW delay ACT(n) to ACT(n+4) delay >= tFAW |
tWR | WRITE to PRE/PREA delay for each bank>= tWL+BL/2+tWR |
tREFI | REFI to REFI delay, for maxminum 8 REFI ban be postponed during operation, if one surrounding send REF number is n: interval between two surrounding REF = n*tREFI, some skew can be exist. and no more than 9*tREFI |