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关于Cortex M3的异常（中断）优先权分组

已有 483 次阅读| 2010-7-3 16:02

5.3.2 Priority grouping
To increase priority control in systems with large numbers of interrupts, the NVIC
supports priority grouping. You can use the PRIGROUP field in the Application
Interrupt and Reset Control Register on page 8-21 to split the value in every PRI_N
field into a pre-emption priority field and a subpriority field. The pre-emption priority
group is referred to as the group priority. Where multiple pending exceptions share the
same group priority, the sub-priority bit field is then used to resolve the priority within
a group. This is referred to as the sub-priority within the group. The combination of the
group priority and the sub-priority is referred to generally as the priority. Where two
pending exceptions have the same priority, the lower pending exception number has
priority over the higher pending exception number. This is consistent with the priority
precedence scheme.

Pre-emption New exception has higher priority than current exception priority or thread and interrupts current flow.
This is the response to a pended interrupt, causing an ISR to be entered if the pended interrupt is higher
priority than the active ISR or thread. When one ISR pre-empts another, the interrupts are nested.
On exception entry the processor automatically saves processor state, which is pushed on to the stack. In
parallel with this, the vector corresponding to the interrupt is fetched. Execution of the first instruction of
the ISR starts when processor state is saved and the first instruction of the ISR enters the execute stage of
the processor pipeline. The state saving is performed over the System bus. The vector fetch is performed
over either the System bus or the DCode bus depending on where the vector table is located, see Vector

Cortex M3的异常（中断）可以被分组为组优先权和子优先权。
组优先权具有抢占优先权特性，子优先权具有响应优先权特性。

具有高抢占优先权的异常（中断）可以打断目前正在处理的异常（中断）响应，形成中断嵌套。反之则不行。

相同优先级组的异常（中断）具有不同的响应优先权，即如果同组内两个异常（中断）都处于带处于待定状态，响应优先权高的异常（中断）会得到响应。

如果两个优先级组的异常（中断）具有相同的组优先权和子优先权，
在待定状态的时候，低异常（中断）编号的异常（中断）具有高的响应优先权，会得到响应。

CM3的Interrupt Priority Registers低8位用于指定优先权，高N位指定组优先权，低8-N为用于指定子优先权。

分组数目N由Application Interrupt and Reset Control Register的8-10位决定