Hspice is a commercially available extended version of the SPICE circuit simulator developed at the University of California at Berkeley.  Compared to verilog-XL, Hspice lets you perform. detailed transistor level simulations. Hspice simulations imitate the actual performance of the circuit when fabricated. However, the accuracy of the transistor level simulations depends on how well each device in the circuit is modeled.

We use Hspice level 49 models for all our transistors in simulation. When using cadence with the NCSU design kit, these model files are automatically selected. In this section, we will perform. transistor level simulation for an inverter schematic we designed earlier in the tutorial.

In the following tutorial we have two different methods to perform. Hspice simulations. Steps 1 through 4 are the same for both methods.
Method 1, which is explained under the Method 1 section following Step 4 uses the Cadence waveform. viewer and result browser for viewing and post processing of the Hspice simulated results.
Method 2, which is explained under the Method 2 section following the description of Method 1, is a more manual approach where the Hspice netlist file is first generated from Cadence and then modified to include additional Hspice statements.  To view the results, we use a much better "Awaves" graphical user interface.
 

1. For every cell that needs to be tested, we will need to generate a test schematic. For an inverter, create another cell called 'inverter_test' in your current library (for the tutorial we assume that the current library is 'ee560'). Create a schematic view for this cell. Refer to "Create Schematics" section of the tutorial on how to create a schematic.  For your convenience, the steps are mentioned again. Click on File -> New -> CellView in the CIW window. Then enter Library Name as ee560, cellname as inverter_test and View Name as Schematic. This should pop-up an empty schematic creation window. In this window, you will generate a schematic as shown below:
 

To generate a schematic like this, you will need to go through the following steps. This assumes that you already have an inverter schematic and its symbol.

1 a. Place an instance for an inverter by pressing 'i'. (How to place an instance has already been discussed in "Create Schematics" section).  Make sure that you choose an inverter symbol from the ee560 library as your instance.

1 b. Place an instance for the piece-wise linear voltage source (vpwl), which you can find in the NCSU_Analog_Parts library under Voltage_Sources. View and edit its properties using 'q'. The vpwl source enables you to specify voltage source as a piece-wise linear curve. Enter the voltages as discrete entries for different time instants.

The above entry specifies voltage source at three points with (time, voltage) values of (0us, 0V), (3us, 0V) and (3.001us, 5V) respectively.
In other words we entered a voltage source with a rise transition from 0 to 5V at 3us, with the rise time of 0.001us.

1 c. Place an instance of a capacitor, which you can find under NCSU_Analog_Parts -> R_L_C -> cap. A capacitor will simulate the effect of capacitive loading from the following stages. For illustration purposes, choose a value of 1pf for the capacitor.
1 d. Label the ground net, as shown in schematic to be gnd!

If you notice, we have created a test setup for the inverter, by giving it an input and having a capacitive load. But we haven't yet mentioned the power supply voltages to be given to the inverter. This is done by explicitly specifying and assigning the power supply to some desired constant DC voltage in the test schematic.

1 e. Place an instance of a DC voltage supply, which you can find under NCSU_Analog_Parts -> Voltage_Sources -> vdc.  In the properties window, set the value of the DC voltage to whatever power supply you desire.  For our purposes, we will set this value to 5V.  Using the wire mode, connect the bottom node of the 5V power supply to the ground net (gnd!) that you just labeled in Step 1 d.  Next, draw an open-ended wire from the top node of the power supply and make it your power line by labeling it as vdd! This will tell Cadence that any other net labeled as vdd! in the test schematic (including those inside any symbol) will automatically be associated with the 5V power supply.

Note:      To print schematics, do the following:

-         -         Design -> Plot -> Submit

-         -         Plot Options

-         -         Select 'Center Plot' and click on 'Fit To Page' button

-         -         Select only 'Send Plot Only to File' and type in directory location and filename. To place the file inside your home directory, syntax is as follows: ~/filename.ps

-         -         To view the file, type 'gs filename.ps' at the Unix xterm prompt. You must be in the same directory as the file.

-         -         To print, type 'lpr filename.ps'. The file will automatically be printed at the CETS office.

To start Hspice, click on Tools ->Analog Environment -> Simulation in the CIW window. If your schematic window is already open, you may click on Tools -> Environment in the schematic window.  A window will pop-up. This window is the Affirma Analog Environment Simulation window.
 
 

2. Click on the Setup -> Design. This will pop-up a window, which should show you the design library as ee560 and the cell name as "inverter_test" for your simulation. If not, update the fields appropriately.

3. Click on Setup -> Simulator/Directory/Host. Enter the fields as shown below. Choose HspiceS as your simulator. The author has chosen to run simulation in the directory /tmp/sameers/hspice_inverter.run1. You may choose any valid pathname and filename as you like.

Note:  When specifying the project directory for any Hspice simulation, instead of choosing some valid directory in your own home account, run the simulation in the /tmp directory.  This is a directory accessible by every engineering student and is used as a temporary file storage directory.  When your Cadence designs and simulations become more and more complicated towards the end of the semester, your accounts could potentially run out of disk quota.  In this case, you will not be able to use Cadence anymore.

4. Click on the second button from the top at the right hand side of the Analog Environment Simulation window. Or you can click on Analyses -> Choose. A menu will pop-up. You can perform. either dc analysis (which lets you sweep a DC voltage source) or you can perform. a transient analysis by choosing tran to observe the output as a function of time. ac and noise analysis is primarily used by analog designers to measure the frequency response and the noise performance of the circuit.   In this tutorial we focus on transient analysis. Enter the time limits for simulation as shown below. Don't forget to choose Enabled at the bottom of the screen.

The above entries ask the circuit to perform. transient simulation from 0 to 5 us with a step interval of 1 us.

Use either Method 1 or Method 2 below after the above step. Method 1 is a cadence environment based spice interface for post processing and viewing of the output results generated from Hspice. Method 2 is an approach where the outputs are viewed and processed outside Cadence.
 

Method 1:

5. Go to simulation menu in the Analog Artist Simulation window and click on Run. This will start simulation. (It is important to understand what Cadence does, when you hit a Run. It first creates a raw netlist having just the top-level instances and the include files. Next it generates a final netlist by bringing in all transistor level details. And finally, it runs the Hspice simulation. You can also go through these steps manually, by first clicking on Simulation  -> Netlist -> Create Raw and then Simulation -> Netlist -> Create Final and finally press Run.  Every step will show you an intermediate netlist output for your review. If you just press Run the first and only time, it will do all the three in one step, without showing you the intermediate netlist output).

 This will start the simulation process.  A menu may pop-up asking you to set a variable "CDS_Netlisting_Mode".
 Just click on "OK".

6.  The CIW window should show "Reading Simulation Data ...... Successful", to ensure that simulation was a success. If not, go to Simulation -> Output Log in your Analog Artist Simulation window to find out what the problem was. Now you can still continue with Cadence to view your results, which is mentioned below or use "awaves" outside of cadence to view your results, not mentioned in the tutorial.

7. Go to Tools -> Calculator in the Analog Environment Simulation Window. A very useful tool "Calculator" will pop-up. It is a very friendly and highly resourceful graphical user interface to view simulation results.

8. Click on browser button in calculator window.  Another window will appear.

Add schematic/psf at the end of the pathname, shown in the above window. Another pathname can also be mentioned in that window to point to the Hspice output data. Usually it is stored in the schematic/psf sub-directory within your main simulation directory. The author will then have his path name as:
/tmp/sameers/inverter_test.run1/inverter_test/hspiceS/schematic/psf

9. Another window will pop-up as shown below.  This window is called the Results Browser. Click on the .tr extension to find results for your transient analysis.

10.  Click on any net name mentioned in that menu. Then go to Calculator window and click on plot. The author has chosen to plot the voltage waveforms at net9 and net12, which correspond to the input and output nodes respectively.   Since net names in this format of numerals may be hard to trace in a bigger circuit, it is a good custom to label all the important nets with sensible names for ease of reference.

The author had clicked on Axes -> To Strip to plot it as two different plots in the same window.
 
 

If you had used erplot instead of plot, it will erase the previous plot before plotting the current node voltage. You can also click on "Help" in the Calculator window, to get help on the other buttons.
 

Method 2:

11.  Go to Simulation -> Netlist -> Create Final in the Analog Environment Simualtion window.
A window will pop-up after few minutes. This is the Hspice netlist file.  Click on File -> Save as in this window to save the netlist file with a .sp extension (as in filename.sp) in your run directory. It is encouraged that you create a separate directory in your home directory to save and run Hspice simulations. The author of the tutorial has saved his netlist file under a new directory named HspiceRun in his home directory.

12.  Once the file is saved, open the file (filename.sp) from the unix prompt using the Emacs editor command. You should see the following lines in your file.

.OPTION INGOLD=2 ARTIST=2 PSF=2
.PROBE=0

Now, do the following:

a. Delete the entire .OPTION statement from the file.
              b. Add a .OPTION POST statement instead.
              c. Add any other Hspice control statements before the .end statement, depending upon the type of analysis and measurement to be carried out.

13.  Once you have completed updating your Hspice file, type hspice filename.sp > filename.lis at the UNIX prompt. The file filename.lis stores the output log of the simulation run. Check if the simulation ran successfully. If there is an error in the simulation, open the filename.lis using the Emacs editor to find out what went wrong.