http://www.edaboard.com/thread63856.html

The historical use of Tie-Lo and Tie-Hi cells is almost as much emotional as it is secular.

The reason I say this is that some people use them religiously without thought as to why. Depending on your process and your design they may or may not be necessary. Most people do not know why they are used.

ESD and Reliability are the right answer. In some processes, the gate oxide is very delicate and sensitive relative to the voltage levels of the chip. That means for any node with a gate tied to a low impedance, such as a GND or VDD, the voltage on the gate is fixed...but what happens if the voltage on the drain or source experienced a surge, over a short period of time, well after enough surges, your oxide reliability fails. Generally these surges are fast impulses, either ESD or ground bounce or some other fast transient impules, because if it was DC...then the chip would be operating outside the limits of the process.

So how does the tie-lo/Hi work, it works by creating a DC level path but a high impedance AC path on the gate oxide, this allows the voltage level on the gate to spike up or down, with voltage surges on its drain and or source, and even though these voltage spikes are capacitively divided between all the nodes, because the gate voltage is allowed to follow or track surges on drains/sources, than the voltage across the delicate oxides are kept within more tolerant levels than if the gate had been hard tied to a low impedance GND/PWR.

This is particularly critical on CDM (charge Device Model) ESD type events for IC's.

For almost this exact reason, you see a lot of 65nm and 45nm (even some 130 and 90nm) process that do not allow LVT decoupling caps with oxides tied directly to a power or ground terminal (gate leakage problems aside...though that is also a factor).

They are not always needed and do tend to take up more area. Know your process, your design and the conditions for your design to determine if you need them or not...when in doubt however, I would recommend using them.

As for how they are designed, there are many formats, the most common being a large resistor in series with the gate, others involving diodes or secondary transistors, etc.

SRFTech