eDRAM就是集成在die内部或者封装在chip内部的DRAM，采用1T1C的结构，可以提供更高的频率和带宽以及集成度。但是集成在die内部制造工艺比较难，封装在片内封装成本比较高。

Due to its one-transistor bit cell, 1T-SRAM is smaller than conventional (six-transistor, or “6T”) SRAM, and closer in size and density to embedded DRAM (eDRAM). At the same time, 1T-SRAM has performance comparable to SRAM at multi-megabit densities, uses less power than eDRAM and is manufactured in a standard CMOS logic process like conventional SRAM.

1T SRAM is built as an array of small banks (typically 128 rows × 256 bits/row, 32 Kbits in total) coupled to a bank-sized SRAM cache and an intelligent controller.

Note that this is not the same as 1T DRAM, which is a "capacitorless" DRAM cell built using the parasitic channel capacitor of SOI transistors rather than a discrete capacitor