module fsm_2
(
input clk,
input rst_n,
input enable,
input [2:0] data_in,
output reg data_out,
output reg state0,
output reg state1,
output reg state2
);
parameter DEFLT = 4'b0001;
parameter IDLE = 4'b0010;
parameter READ = 4'b0100;
parameter WRITE = 4'b1000;
reg [3:0] cur_state;
reg [3:0] next_state;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 1'b0)
cur_state <= IDLE;
else
cur_state <= next_state;
end
always @(*)
begin
case (cur_state)
IDLE :
begin
state1 = 1'b0;
state2 = 1'b0;
if (enable)
next_state = READ;
else
next_state = IDLE;
if (enable == 1'b1)
begin
state0 = 1'b1;
data_out = data_in[0];
end
else
begin
state0 = 1'b0;
data_out = 1'b0;
end
end
READ :
begin
state0 = 1'b0;
state2 = 1'b0;
if (enable)
next_state = WRITE;
else
next_state = READ;
if (enable == 1'b1)
begin
state1 = 1'b1;
data_out = data_in[1];
end
else
begin
state1 = 1'b0;
data_out = 1'b0;
end
end
WRITE :
begin
state0 = 1'b0;
state1 = 1'b0;
if (enable == 1'b1)
next_state = IDLE;
else
next_state = WRITE;
if (enable == 1'b1)
begin
state2 = 1'b1;
data_out = data_in[2];
end
else
begin
state2 = 1'b0;
data_out = 1'b0;
end
end
default :
begin
next_state = DEFLT;
state0 = 1'b0;
state1 = 1'b0;
state2 = 1'b0;
data_out = 1'b0;
end
endcase
end
endmodule
//--------------------------------------------------------------------------------------------
module fsm_3
(
input clk,
input rst_n,
input enable,
input [2:0] data_in,
output reg data_out,
output reg state0,
output reg state1,
output reg state2
);
parameter DEFLT = 4'b0001;
parameter IDLE = 4'b0010;
parameter READ = 4'b0100;
parameter WRITE = 4'b1000;
reg [3:0] cur_state;
reg [3:0] next_state;
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 1'b0)
cur_state <= IDLE;
else
cur_state <= next_state;
end
always @(*)
begin
case (cur_state)
IDLE:
begin
if (enable)
next_state <= READ;
else
next_state <= IDLE;
end
READ:
begin
if (enable)
next_state <= WRITE;
else
next_state <= READ;
end
WRITE:
begin
if (enable == 1'b1)
next_state <= IDLE;
else
next_state <= WRITE;
end
default: next_state <= DEFLT;
endcase
end
always @ (posedge clk or negedge rst_n)
begin
if (rst_n == 1'b0)
state0 <= 1'b0;
else if ( (cur_state == IDLE) && (enable == 1'b1) )
state0 <= 1'b1;
else
state0 <= 1'b0;
end
always @ (posedge clk or negedge rst_n)
begin
if (rst_n == 1'b0)
state1 <= 1'b0;
else if ( (cur_state == READ) && (enable == 1'b1) )
state1 <= 1'b1;
else
state1 <= 1'b0;
end
always @ (posedge clk or negedge rst_n)
begin
if (rst_n == 1'b0)
state2 <= 1'b0;
else if ( (cur_state == WRITE) && (enable == 1'b1) )
state2 <= 1'b1;
else
state2 <= 1'b0;
end
always @ (posedge clk or negedge rst_n)
begin
if (rst_n == 1'b0)
data_out <= 1'b0;
else if (enable == 1'b1)
begin
case(cur_state)
IDLE: data_out <= data_in[0];
READ: data_out <= data_in[1];
WRITE: data_out <= data_in[2];
default: data_out <= 1'b0;
endcase
end
else
data_out <= 1'b0;
end
endmodule