//pll_locked_final = (pll_locked AND pll_locked_alt)
//the time between 5&6 is 4us
//The minimum pulse width for gxb_powerdown signal is 100 ns
//The minimum pulse width for tx_digital_rst, rx_analog_rst and rx_digital_rst
//is two parallel clock cycles
//
//Reset Sequence (1 > 2 > 3 > 4 > 5 > 6)
//input                         1    2
//gxb_pwr_dn                ____|----|__________________________________________
//                                              4
//tx_digital_rst            ____|---------------|_______________________________
//                                              4
//rx_analog_rst             ____|---------------|_______________________________
//                                                           5    6
//rx_digital_rst            ____|---------------------------------|_____________
//                                                           |
//output                                                     |
//pll_locked                _______________|-----------------|------------------
//                                                           |
//pll_locked_alt            ___________|---------------------|------------------
//                                           3               |
//pll_locked_final          _________________|---------------|------------------
//                                                           |
//rx_freq_locked            _________________________________|------------------
//                                                           5
`timescale 1ns/1ns
module alt_gxb_rst_ctrl
    (
    input                   clk_50m,
    input                   rst_clk_50m,

    input                   gxb_power_down,
    input                   gxb_channel_rst,
    input                   pll_locked,
    input                   rx_pll_locked,
    input                   rx_freq_locked,

    output  reg             tx_digital_rst,
    output  reg             rx_analog_rst/* synthesis syn_preserve = 1*/,
    output  reg             rx_digital_rst

    );

reg     [6:0]   cnt_pwdn_time;
reg     [1:0]   pll_locked_dly;
reg     [1:0]   rx_pll_locked_dly;
reg     [2:0]   rx_freq_locked_dly;
reg     [9:0]   cnt_rx_digital_rst;

wire            gxb_pwdn_rise;

////////////////////////////////////////////////////////////////////////////////
//gxb power done control
//always @ (posedge clk_50m or posedge rst_clk_50m)
//begin
//    if (rst_clk_50m == 1'b1)
//        gxb_power_down_dly1 <= 1'b0;
//    else
//        gxb_power_down_dly1 <= gxb_power_down;
//end

//assign gxb_pwdn_rise = gxb_power_down && (~gxb_power_down_dly1);

//always @ (posedge clk_50m or posedge rst_clk_50m)
//begin
//    if (rst_clk_50m == 1'b1)
//        cnt_pwdn_time <= 7'd0;
//    else if (gxb_pwdn_rise == 1'b1)
//        cnt_pwdn_time <= 7'd0;
//    else
//        cnt_pwdn_time <= cnt_pwdn_time + {6'd0,~(&cnt_pwdn_time)};
//end
//
//always @ (posedge clk_50m or posedge rst_clk_50m)
//begin
//    if (rst_clk_50m == 1'b1)
//        gxb_pwr_dn <= 1'b1;
//    else if (cnt_pwdn_time != 7'h7f)
//        gxb_pwr_dn <= 1'b1;
//    else
//        gxb_pwr_dn <= 1'b0;
//end
////////////////////////////////////////////////////////////////////////////////

always @ (posedge clk_50m or posedge rst_clk_50m)
begin
    if (rst_clk_50m == 1'b1)
        pll_locked_dly <= 2'b00;
    else
        pll_locked_dly <= {pll_locked_dly[0],pll_locked};
end

////////////////////////////////////////////////////////////////////////////////
//tx digital reset
always @ (posedge clk_50m or posedge rst_clk_50m)
begin
    if (rst_clk_50m == 1'b1)
        tx_digital_rst <= 1'b1;
    else if ((gxb_power_down == 1'b1) || (gxb_channel_rst == 1'b1) || (pll_locked_dly[1] == 1'b0))
        tx_digital_rst <= 1'b1;
    else
        tx_digital_rst <= 1'b0;
end
////////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////
//rx analog reset
always @ (posedge clk_50m or posedge rst_clk_50m)
begin
    if (rst_clk_50m == 1'b1)
        rx_analog_rst <= 1'b1;
    else if ((gxb_power_down == 1'b1) || (gxb_channel_rst == 1'b1) || (pll_locked_dly[1] == 1'b0))
        rx_analog_rst <= 1'b1;
    else
        rx_analog_rst <= 1'b0;
end
////////////////////////////////////////////////////////////////////////////////

////////////////////////////////////////////////////////////////////////////////
//rx digital reset
always @ (posedge clk_50m or posedge rst_clk_50m)
begin
    if (rst_clk_50m == 1'b1)
        rx_pll_locked_dly <= 2'b00;
    else
        rx_pll_locked_dly <= {rx_pll_locked_dly[0],rx_pll_locked};
end

always @ (posedge clk_50m or posedge rst_clk_50m)
begin
    if (rst_clk_50m == 1'b1)
        rx_freq_locked_dly <= 3'd0;
    else
        rx_freq_locked_dly <= {rx_freq_locked_dly[1:0],rx_freq_locked};
end

wire            rx_freq_locked_rise;
assign rx_freq_locked_rise = ~rx_freq_locked_dly[2] & rx_freq_locked_dly[1];

always @ (posedge clk_50m or posedge rst_clk_50m)
begin
    if (rst_clk_50m == 1'b1)
        cnt_rx_digital_rst <= 10'd0;
    else if ((rx_pll_locked_dly[1] == 1'b1) && (rx_freq_locked_dly[2] == 1'b1))
    begin
        if (rx_freq_locked_rise == 1'b1)
            cnt_rx_digital_rst <= 10'd0;
        else
            cnt_rx_digital_rst <= cnt_rx_digital_rst + {9'd0,~(&cnt_rx_digital_rst)};
    end
    else
        cnt_rx_digital_rst <= 10'd0;
end

always @ (posedge clk_50m or posedge rst_clk_50m)
begin
    if (rst_clk_50m == 1'b1)
        rx_digital_rst <= 1'b0;
    else if ((gxb_power_down == 1'b1) || (gxb_channel_rst == 1'b1) || (cnt_rx_digital_rst != 10'h3ff))
        rx_digital_rst <= 1'b1;
    else
        rx_digital_rst <= 1'b0;
end
////////////////////////////////////////////////////////////////////////////////

endmodule