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格雷码与二进制码的互相转换

已有 778 次阅读| 2012-1-1 21:10 |个人分类:FPGA_Verilog

module bin2gray
    #(
    parameter SIZE = 8, // this module is parameterizable
    )
    (
    input   [SIZE-1:0] bin,
    output [SIZE-1:0] gray
    );

genvar i;
generate
    for (i=0; i<SIZE; i=i+1)
    begin:bit
        if (i == SIZE-1)
            assign gray[i] = bin[i];
        else
            assign gray[i] = ^bin[i+1:i];
    end
endgenerate

endmodule

module gray2bin
    #(
    parameter SIZE = 8, // this module is parameterizable
    )
    (
    output [SIZE-1:0] bin,
    input   [SIZE-1:0] gray
    );

genvar i;
generate
    for (i=0; i<SIZE; i=i+1)
    begin:bit
        assign bin[i] = ^gray[SIZE-1:i];
    end
endgenerate

endmodule