在设计中经常会用于FPGA内部的一些硬件资源，比如芯片内部的RAM，DSP，PLL等资源在
一个设计中可能会使用到多块位宽，深度不同的RAM，如果每次都使用厂家提供的
megawiz工具去产生所需要的各个RAM，这样就会产生很多个代码。
    本工程是一个用megawiz生成的8bit位宽，深度64的RAM

// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module dpram_8x64_1 (
    aclr,
    clock,
    data,
    rdaddress,
    rden,
    wraddress,
    wren,
    q);

    input      aclr;
    input      clock;
    input    [7:0]  data;
    input    [5:0]  rdaddress;
    input      rden;
    input    [5:0]  wraddress;
    input      wren;
    output    [7:0]  q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
    tri0      aclr;
    tri1      clock;
    tri1      rden;
    tri0      wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif

    wire [7:0] sub_wire0;
    wire [7:0] q = sub_wire0[7:0];

    altsyncram    altsyncram_component (
                .wren_a (wren),
                .aclr0 (aclr),
                .clock0 (clock),
                .address_a (wraddress),
                .address_b (rdaddress),
                .rden_b (rden),
                .data_a (data),
                .q_b (sub_wire0),
                .aclr1 (1'b0),
                .addressstall_a (1'b0),
                .addressstall_b (1'b0),
                .byteena_a (1'b1),
                .byteena_b (1'b1),
                .clock1 (1'b1),
                .clocken0 (1'b1),
                .clocken1 (1'b1),
                .clocken2 (1'b1),
                .clocken3 (1'b1),
                .data_b ({8{1'b1}}),
                .eccstatus (),
                .q_a (),
                .rden_a (1'b1),
                .wren_b (1'b0));
    defparam
        altsyncram_component.address_aclr_b = "CLEAR0",
        altsyncram_component.address_reg_b = "CLOCK0",
        altsyncram_component.clock_enable_input_a = "BYPASS",
        altsyncram_component.clock_enable_input_b = "BYPASS",
        altsyncram_component.clock_enable_output_b = "BYPASS",
        altsyncram_component.intended_device_family = "Cyclone III",
        altsyncram_component.lpm_type = "altsyncram",
        altsyncram_component.numwords_a = 64,
        altsyncram_component.numwords_b = 64,
        altsyncram_component.operation_mode = "DUAL_PORT",
        altsyncram_component.outdata_aclr_b = "CLEAR0",
        altsyncram_component.outdata_reg_b = "CLOCK0",
        altsyncram_component.power_up_uninitialized = "FALSE",
        altsyncram_component.rdcontrol_reg_b = "CLOCK0",
        altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
        altsyncram_component.widthad_a = 6,
        altsyncram_component.widthad_b = 6,
        altsyncram_component.width_a = 8,
        altsyncram_component.width_b = 8,
        altsyncram_component.width_byteena_a = 1;

endmodule

    从上面的代码可以看到，这个RAM实际上是例化了一个altsyncram的RAM器件，如果需要例
化多个不同位宽和深度的RAM，直接对其进行参数化处理即可，这样就不会产生多个代码
文件.
    对于其它的一些IP CORE也可以用类似的方法生成。