`timescale 1ns/1ns
module test_for_lp
    (
    input                   clk,
    input                   rst,
    output  reg     [7:0]   en
    );
    
reg     [5:0]   cnt;
always @ (posedge clk or posedge rst)
begin
    if (rst == 1'b1)
        cnt <= 6'd0;
    else
        cnt <= cnt + 6'd1;
end
//使用for语句简化书写后的代码
genvar  i;
generate
    for(i=0;i<=7;i=i+1)
    begin:en_gen
        always @ (posedge clk or posedge rst)
        begin
            if (rst == 1'b1)
                en[i] <= 1'b0;
            else if (cnt == i*8)
                en[i] <= 1'b1;
            else
                en[i] <= 1'b0;
        end
    end
endgenerate
//简化前的代码
//always @ (posedge clk or posedge rst)
//begin
//    if (rst == 1'b1)
//        en[0] <= 1'b0;
//    else if (cnt == 6'd0)
//        en[0] <= 1'b1;
//    else
//        en[0] <= 1'b0;
//end
//
//    .
//    .
//    .
//  
//always @ (posedge clk or posedge rst)
//begin
//    if (rst == 1'b1)
//        en[7] <= 1'b0;
//    else if (cnt == 6'd56)
//        en[7] <= 1'b1;
//    else
//        en[7] <= 1'b0;
//end  
  
endmodule