Mbistarchitecture产生各种类型的memory bist

1.       ROM bist

ROM由于只能读，所以不能任意的输入特定的测试向量，但是通过读出ROM内容，逐个地址比较的方法对于大容量的ROM非常的浪费时间，于是有人提供了一种算法，即读出一个地址，该地址的内容做校验（CRC?），校验值参与下一个地址的校验，扫描所有的地址之后得到一个最终的校验值，将这个值通过scan port shift出来进行比较。也可以内部比较这个值，输出fail/pass结果。请看这个例子。

model DROM (Q, CLK, CEN, A)

(

bist_definition (

        address A(array=11:0;);

        data_out Q(array=63:0;);

        clock CLK high;

        output_enable CEN low;

        tech = smic18;

        vendor = arm;

        version = "1.0";

        message = "synchronous 4096X64 ROM";

        address_size = 12;

        min_address = 0;

        max_address = 4095;

        data_size = 64;

        read_port (

                read_cycle (

                        change A;

                        assert CEN;

                        wait;

                        wait;

                        expect Q move;

                        )

                )

        )

)

以上是以mentor语法描述的ROM，我们产生其bist生成脚本

// rom_bist.do

reset state

load lib ../bist_model/DROM.vm

add memory model DROM

add memory model DROM_B3

add memory model IROM_B1

add memory model IROM_B1_MR

add memory model IROM_B2

add memory model IROM_B3

setup mbist algorithms Rom2

set design name controller -module SPROM_4096X64_bist

set file naming -bist_model ../result/SPROM_4096X64_bist.v

set file naming -connected_model ../result/SPROM_4096X64_bist_con.v

set file naming -testbench ../result/SPROM_4096X64_bist_tb.v

set file naming -script. ../result/SPROM_4096X64_bist.v_dcscript

set file naming -ctdl ../result/SPROM_4096X64_bist.v_ctdf

set file naming -wgl ../result/SPROM_4096X64_bist.v_wgl

run

save bist -verilog -script. -replace

exit –discard

// run_bist

mbistarchitect -bistgen \

-dofile ./rom_bist.do \

-logfile ./rom_bist.log -replace \

-nogui

运行run_bist即可得到ROM bist的rtl文件。

2.       SRAM bist

SRAM是一种单口的静态RAM，可以读写，所以我们可以控制往RAM中写入的内容，然后读出来比较。这类bist算法很多，常用March2算法，可以检查address decoder faults (AF), stuck at faults (SAF),transition faults (TF), stuck open faults (SOF), inversion coupling faults (CFin), and linkedidempotent coupling faults (CFid)这些问题。

下面给出一个model的例子，运行脚本和ROM类似。

model SPRAM_512X32 (Q,CLK,CEN,WEN,A,D,OEN)

(

bist_definition (

        address A(array=8:0;);

        data_in D(array=31:0;);

        data_out Q(array=31:0;);

        clock CLK high;

        chip_enable CEN low;

        write_enable WEN low;

        dont_touch OEN high;

        tech = smic18;

        vendor = ARM;

        version = "1.0";

        message = "synchronous 512X32 RAM";

        address_size = 9;

        min_address = 0;

        max_address = 511;

        data_size = 32;

        read_write_port (

                write_cycle (

                        change A;

                        change D;

                        assert CEN;

                        assert WEN;

                        wait;

                        )

                read_cycle (

                        change A;

                        assert CEN;

                        wait;

                        wait;

                        expect Q move;

                        )

                )

        )

)

3．DRAM

DRAM是双口的RAM，一般有两种类型，第一种是两套接口都可以完成读写操作，第二种是一套口专门读，另一套口专门写，所用的bist算法与SRAM相同。下面给出一个例子。

model DPRF_128X32 (QA,AA,CLKA,CENA,AB,DB,CLKB,CENB)

(

bist_definition (

        address AA(array=6:0;);

        address AB(array=6:0;);

        data_in DB(array=31:0;);

        data_out QA(array=31:0;);

        clock CLKA high;

        clock CLKB high;

        read_enable CENA low;

        write_enable CENB low;

        tech = smic18;

        vendor = ARM;

        version = "1.0";

        message = "synchronous 128X32 dual port RAM";

        address_size = 7;

        min_address = 0;

        max_address = 127;

        data_size = 32;

        write_port (

                write_cycle (

                        change AB;

                        change DB;

                        assert CENB;

                        wait;

                        )

        )

        read_port (

                read_cycle (

                        change AA;

                        assert CENA;

                        wait;

                        wait;

                        expect QA move;

                        )

                )

        )

)

总结：Mentor的工具在产生bist的时候比较强大，美中不足的是需要我们用它自己的语法来描述memory对象，不过好在其语法比较简单。所以model能不能写的符合要求，能不能与vendor提供的model一直十分的重要，也是要特别注意的地方。