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（转）FPGA的速度等级（speed grade）

已有 6654 次阅读| 2010-5-5 10:58 |个人分类:FPGA硬件知识

XILINX公司FPGASpartan 3E系列XC3S500E速度等级为4.但一直不知道是什么意思.

通过学习知道,

(1)CPLD与FPGA的速度等级定义的区别

(2)不同的公司FPGA的速度等级

(3)同一个公司的不同时期的定义也是不一样的,如XLINX公司

具体内容可以参考以下材料.也可以在GOOGLE里输入 FPGA SPEED GRADE

(4)对于xilinx公司的FPGA的速度等级定义，个人观点：它不是以前所定义的其内部的一些逻辑单元信号传播所花的时间，而是一类内部逻辑器件的运行速度，这些逻辑器件运行时满足一定要求的时钟频率．它没有具体的物理的数据意义，只是一类内部逻辑器件的运行速度的的代号．

There is no consistent definition of a speed grade for all devices. Even for Xilinx,

speed grades mean different things depending on if you are referring to a FPGA or a CPLD. For CPLDs, speed grades represent the time it takes for logic to go through the device (eg. in <= out). So a -10 device means that the device is guaranteed to send a signal from an input pin thru to an output pin in under 10 nS. So for CPLDs, the lower the number, the faster the part is. This is standard for CPLDs across all vendors so this can be used for device comparison purposes.

what is the valve of standard grade(FPGA)

However for FPGAs, they don't use the same definition for speed grade. Originally speed grades for FPGAs represented the time through a look up table but now the speed grade doesn't actually repesent a timing path. I am not sure if it is the same for other vendors, but for Xilinx FPGAs higher numbers are faster. Each speed grade increment is ~15% faster than the one before it. So a -5 is 10% faster than a -4 speed grade.

Determining the speed grade of Xilinx devices

I am having some trouble understanding the numbering system Xilinx uses for speed grade. Could someone explain what the numbers are and how to tell which speed grade is installed on my XS40. FWIW I have an XC4010XL FPGA. The available speed grade choices are -1, -2 -3, or -09.

You usually see the speed grade imprinted on the chip on a line by itself. For an XC4000, you might see "3C" printed on the chip. That means the chip has speed grade -3. (I think the "C" stands for commercial temperature range.)

For XC4000 devices, the number is roughly equivalent to the propagation delay through a CLB. So a -3 speed grade implies 3 ns of delay through a level of logic, -2 means 2 ns. Don't be mislead by -09, it actually means 0.9 ns of delay.

The situation changes with Spartan and Virtex devices. Now a larger number means the device is faster.

Reference : http://www.xess.com/faq/M0000236.HTM

Question:

From: vlsigeek
Date Posted : 12/11/2004 4:42:49 AM Hi guys,

What is the speed grade in FPGA. What it tells actually.

Thanks in advance,

Soundar

Comments:

From: vlsi_giant
Posted : 12/27/2004 12:54:29 AM Hi
It is actually the min I/O delay for that device.
Ex: for altera MAX device EPM7128... -15
this -15 indicates this device has min of 15 ns. i/o delay.

yogesh

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speed grade

Category: FPGA

Question:

From: surekha29
Date Posted : 7/19/2006 5:19:41 AM While using xilinx synthesis tool, in the synthesis reports I found a term called speed grade : -6, what does this actually mean??

Comments:

From: muthu_kumar
Posted : 7/20/2006 12:53:49 AM Hi,
Use this field to test a speed grade with your design. Changing the speed grade helps determine a need to target a faster device to meet your timing requirements, or if using a slower speed grade still meets timing constraints. Select a speed grade from the pull-down list, which contains the available speed grades for the target device.

Changing the speed grade in the Options tab tests it with the design; it does not change the speed grade in your FPGA design file.
regards
muthukumar.p

From: vikas
Posted : 7/27/2006 6:06:01 AM THE FREQUENCY OF DESIGN DEPENDS UPON SELECTED DEVICESPEED GRADE.
suppose u have design that is working on 50 mhz,with a device whose speed grade is 6.
now if u want to work at 70 Mhz frequency.and with speed grade 6 u r not acheving that much frequency with that device.then if u take same device with more speed grade then this its sure that ur design fequncy will also increase but it is more costly then then the earlier.

if still have any doubt ask dont hesitate

v.lakhanpal@coraltele.com
vikas lakhanpal
engineer
vlsi designs
coral telecom

From: vikas
Posted : 7/27/2006 6:07:11 AM i think that is the importance of speed grade.

From: vikas
Posted : 7/27/2006 6:07:13 AM i think that is the importance of speed grade.

From: surekha29
Posted : 7/28/2006 2:20:34 AM Thanks for ur comments Muthu Kumar and Vikas.
In my search I have found my answer, n thought of sharing...

Internal frequency is the speed at which CPLDs/FPGAs can perform. operations or transfer data internally. The propagation delay is the time interval between the application of an input signal and the occurrence of the corresponding output in a logic circuit. Speed grade indicates the delay in nanoseconds (ns) through a macrocell in the device. For example, a device with a speed grade of –10 has a delay of 10 ns through a macrocell. Devices with low speed grade numbers run faster than devices with high-speed grade numbers.

speed grade of -09 implies a delay of 0.9ns.

From: muthu_kumar
Posted : 7/30/2006 11:23:51 PM Hi surekha,Where u get these ideas?provide the source. i have doubt about your answers.myself and vikas going into the same direction i.e when the device speed grade is increase then the speed of the device also increase.but your answer is different.I warm welcome to all the readers.pls share your points about this question.
regards
muthukumar.p

From: surekha29
Posted : 7/31/2006 2:12:06 AM Hello,
I have seen the details at the following links.

http://cpld.globalspec.com/
http://www.altera.com/products/devices/dev-format.html
http://cpld.globalspec.com/LearnMore/Semiconductors/Programmable_Logic_Devices/CPLD

I hope the definition of speed grade for FPGA and CPLD are the same. I think the minus indicates the samething, i.e., as the delay increases the speed(frequency) reduces.

From: muthu_kumar
Posted : 7/31/2006 11:44:50 PM Hi thanks ,to day i got the new idea from u.
xilinx fpga point of view -7 speed grade device faster than -6 speed grade device.
But altera cpld point of view -10 speed grade device slower than -9 speed grade device.
ok
-10 and -9 are denotes the macrocell propagation delay.
but if u know any specification of -7 or -6 in FPGA.Anybody knows pls let me know.
regards
muthukumar.p

From: gargji
Posted : 8/2/2006 4:58:03 AM Hi Muthu,
I can give you some more clearification about FPGA speed grades.
In an FPGA the fabricator devides the devices in to some categories. Speed grade -7 means that there is a range of macrocell delay in FPGA which is kept in this category.
But in cplds -10 means the macrocell delay is 10 ns.
Hope the same is helpfull.
rgds

From: manish.
Posted : 9/2/2006 5:15:56 PM surekha n all comment after checking this site

http://www.xess.com/faq/M0000236.HTM

From: gauravkshri
Posted : 11/9/2006 1:14:49 AM hi guys,
I just read ur comments.
If I have been told to describle Speed grade in a sentence,I would say " Its a minimum i/o delay".
This means a signal will take atleast this much of time to travel from i/p to o/p.

From: gauravkshri
Posted : 11/9/2006 1:21:26 AM hi,
You usually see the speed grade imprinted on the chip on a line by itself. For an XC4000, you might see "3C" printed on the chip. That means the chip has speed grade -3. (I think the "C" stands for commercial temperature range.)

For XC4000 devices, the number is roughly equivalent to the propagation delay through a CLB. So a -3 speed grade implies 3 ns of delay through a level of logic, -2 means 2 ns. Don't be mislead by -09, it actually means 0.9 ns of delay.

The situation changes with Spartan and Virtex devices. Now a larger number means the device is faster.

http://www.xess.com/faq/M0000236.HTM