// verilogA for mu2803_cmf, adc_8bit, veriloga

`include "constants.vams"

`include "disciplines.vams"

`define MSB 7

`define LSB 0

`define MMASK 1

`define FULLSCALE (1<<(`MSB+1))

module adc_8bit(vd, vclk, vinp, vinn);  

output     [`MSB:`LSB] vd;  

electrical [`MSB:`LSB] vd;  

input      vclk;  

electrical vclk;  

input      vinp;  

electrical vinp;  

input      vinn;  

electrical vinn;  

parameter real    trise    = 1n from [0:inf);  

parameter real    tfall    = 1n from [0:inf);  

parameter real    tdel     = 0  from [0:inf);  

parameter real    vhi      = 3;  

parameter real    vlo      = 0;  

parameter real    vth      = 1.5;  

parameter real    vref     = 1.0;  

parameter integer bipolar  = 0 from [0:1];  

parameter integer sedge    = 1 from [-1:1];  

parameter integer freeRun  = 0 from [0:1];  

integer vid[`MSB:`LSB];  

integer i;  

integer digval;  

integer fullscale;  

integer index;  

real    lsb;  

real    digMin;  

real    digMax;  

real    vlsb [0: `FULLSCALE];  

real    vinint;  

Analog begin    

@(initial_step) begin      

fullscale = `FULLSCALE;       

lsb       = vref/fullscale;      

if (bipolar) begin        

digMin = -fullscale/2;        

digMax = (fullscale/2 - 1);      

end

else begin        

digMin = 0.0;        

digMax = (fullscale - 1);      

end // if bipolar      

vlsb[0] = digMin*lsb-0.5*lsb;      

for (i=1; i<=`FULLSCALE; i=i+1)        

vlsb[i] = vlsb[i-1] + lsb;    

end    

if (V(vinp,vinn) >= vref ) vinint = V(vinp,vinn) - vref;   

if (V(vinp,vinn) >= 0) vinint = V(vinp,vinn);    

else vinint = 128 - V(vinp,vinn);    

if(analysis("static", "pss")) begin      

digval = max(min(floor((vinint+0.5*lsb)/lsb), digMax), digMin);     

for (i = `MSB; i >= `LSB ; i = i - 1)         

vid[i]  =  ( ( digval  &  (`MMASK << i) ) == 0 ) ? vlo : vhi ;   

end    

index  = max(min(floor((vinint - digMin*lsb)/lsb), `FULLSCALE-1), 0);   

@(   cross((1-freeRun)*(V(vclk)       -  vth           ), sedge, 1n, 0.01*lsb)      

or cross(100*freeRun*(vinint - (vlsb[index+1]        )), +1  , 1n, 0.01*lsb)      

or cross(100*freeRun*(vinint - (vlsb[index+1]-lsb*0.5)),  0  , 1n, 0.01*lsb)       

or cross(100*freeRun*(vinint - (vlsb[index+0]        )), -1  , 1n, 0.01*lsb)      

) begin      

digval = max(min(floor((vinint+0.5*lsb)/lsb), digMax), digMin);     

for (i = `MSB; i >= `LSB ; i = i - 1)         

vid[i]  =  ( ( digval  &  (`MMASK << i) ) == 0 ) ? vlo : vhi ;    

end         

generate i (`MSB , `LSB)       

V(vd[i]) <+ transition( vid[i], tdel, trise, tfall );  

end

endmodule