今天终于发现一个4510bootloader的网页http://twentyone.bokee.com

写的还不错值的学习以下。

希望能运转起4510的网络控制器！

*********************************************************************

init.s文件

;**************************************************************
; 
; This an simple implementation of  bootloader for S3C4510B
; Hope it is useful to you.
; 
; Enjoy it!
;
;**************************************************************

 
        AREA    Init, CODE, READONLY
  CODE32
  GET snds.s
  
        ENTRY

start

;Part 1
;***************************************************************
;disable interrupts in CPU and switch to SVC32 mode

 MRS r0, cpsr
 BIC r0, r0, #MASK_MODE
 ORR r0, r0, #MODE_SVC32
 ORR r0, r0, #I_BIT
 ORR r0, r0, #F_BIT
 MSR cpsr_c, r0

 LDR r2, =ARM7_INTMASK    ;R2->interrupt controller
 MVN r1, #0       ;&FFFFFFFF
 STR r1, [r2]      ;disable all interrupt soucres

 LDR r2, =ARM7_INTPEND    ;R2->interrupt pend register.
 MVN r1, #0       ;&FFFFFFFF
 STR r1, [r2]      ;clear all interrupt flags.

;Part 2
;****************************************************************

 LDR r0, =ARM7_SYSCFG
 LDR r1, =0x87ffffA0    ;config SYSCFG
 STR r1, [r0]      ;Cache & WB disabled

;Part 3
;***************************************************************
; Import some important variables for later use

    IMPORT |Image$$RO$$Base|   
 IMPORT |Image$$RO$$Limit|  
 IMPORT |Image$$RW$$Base|  
 IMPORT |Image$$RW$$Limit|  
 IMPORT |Image$$ZI$$Base|  
 IMPORT |Image$$ZI$$Limit|

;Part 4
;****************************************************************
;Initalize the memory as followa:
; FLASH   @ 0  ~ 2 M
; SDRAM   @ 2  ~ 18M

 LDR r1, =rEXTDBWTH     ;EXTDBWTH            
 LDR r2, =rROMCON0      ;ROMCON0 @ 0M ~ 2M 
 LDR r3, =rROMCON1    ;ROMCON1 @ DISABLED
 LDR r4, =rROMCON2    ;ROMCON1 @ DISABLED
 LDR r5, =rROMCON3    ;ROMCON1 @ DISABLED
 LDR r6, =rROMCON4    ;ROMCON1 @ DISABLED
 LDR r7, =rROMCON5    ;ROMCON1 @ DISABLED
 LDR r8, =rSDRAMCON0    ;SDRAMCON0  @ 2M ~ 18M
 LDR r9, =rSDRAMCON1    ;SDRAMCON1  @ DISABLED
 LDR r10,=rSDRAMCON2    ;SDRAMCON2  @ DISABLED
 LDR r11,=rSDRAMCON3    ;SDRAMCON3  @ DISABLED
 LDR r12,=rSREFEXTCON   
 
 LDR r0, =ARM7_EXTDBWTH    
 STMIA r0, {r1-r12}

;Part 5
;***************************************************************
;Self copy from FLASH to SDRAM

 LDR  r0, =|Image$$RO$$Base|     
 LDR  r1, =|Image$$RO$$Limit|     
 LDR  r2, =|Image$$RW$$Base|     
 LDR  r3, =|Image$$RW$$Limit|    

 SUB  r1, r1, r0
 SUB  r3, r3, r2
 ADD  r1, r1, r3
 
 LDR  r2, =0x200000   ;@2M

 
COPY
 LDR  r3, [r0], #4
 STR  r3, [r2], #4
 SUBS r1, r1,   #4
 BNE  COPY

 
;Part 6
****************************************************************
;Remap the memory
;  FLASH @ 16 ~ 18M
;  SDRAM @ 0  ~ 16M

 
 LDR r1, =rEXTDBWTH_R    ;EXTDBWTH            
 LDR r2, =rROMCON0_R     ;ROMCON0 @ 16M ~ 18M 
 LDR r3, =rROMCON1_R    ;ROMCON1 @ DISABLED
 LDR r4, =rROMCON2_R    ;ROMCON2 @ DISABLED
 LDR r5, =rROMCON3_R    ;ROMCON3 @ DISABLED
 LDR r6, =rROMCON4_R    ;ROMCON4 @ DISABLED
 LDR r7, =rROMCON5_R    ;ROMCON4 @ DISABLED
 LDR r8, =rSDRAMCON0_R   ;SDRAMCON0  @ 0M ~ 16M
 LDR r9, =rSDRAMCON1_R   ;SDRAMCON1  @ DISABLED
 LDR r10,=rSDRAMCON2_R   ;SDRAMCON2  @ DISABLED
 LDR r11,=rSDRAMCON3_R   ;SDRAMCON3  @ DISABLED
 LDR r12,=rSREFEXTCON_R   

 LDR r0, =ARM7_EXTDBWTH    
 STMIA r0, {r1-r12}
 

;Part 7
;*****************************************************************
; Copy RW & ZI to SDRAM

 LDR r0, =|Image$$RO$$Limit|  
 LDR r1, =|Image$$RW$$Base|   
 LDR r3, =|Image$$ZI$$Base|   

 CMP r0, r1
 BEQ %1
 
0  CMP r1, r3       ; Copy init data
 LDRCC r2, [r0], #4
 STRCC r2, [r1], #4
 BCC %0

1  LDR r1, =|Image$$ZI$$Limit|  ; Top of zero init segment
 MOV r2, #0

2  CMP r3, r1       ; Zero init
 STRCC r2, [r3], #4
 BCC %2

;Part 8
;***********************************************************************
;Set stack pointer & jump to c function

 LDR  sp, =0x800000

 IMPORT loadkernel
 LDR  pc, =loadkernel

        END

********************************************************************************

*********************************     ******************************************

snds.s文件

;/*************************************************************************/
;/* Format of the Program Status Register                                 */
;/*************************************************************************/
;/*                                                                       */
;/* 31  30  29   28         7   6   5   4   3   2   1   0                 */
;/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+               */
;/*| N | Z | C | V |      | I | F | T |     M4 ~ M0       |               */
;/*+---+---+---+---+--ss--+---+---+---+---+---+---+---+---+               */
;/*                                                                       */
;/* Processor Mode and Mask                                               */
;/*                                                                       */
;/*************************************************************************/
;

Mode_USR        EQU     0x10
Mode_FIQ        EQU     0x11
Mode_IRQ        EQU     0x12
Mode_SVC        EQU     0x13
Mode_ABT        EQU     0x17
Mode_UND        EQU     0x1B
Mode_SYS        EQU     0x1F

MASK_MODE  EQU  0x0000003F
MODE_SVC32  EQU  0x00000013

I_BIT           EQU     0x80 ; when I bit is set, IRQ is disabled
F_BIT           EQU     0x40 ; when F bit is set, FIQ is disabled

ASIC_BASE     EQU  0x03ff0000

;SYSTEM MANAGER REGISTERS
ARM7_SYSCFG     EQU  (ASIC_BASE+0x0000)
ARM7_CLKCON   EQU  (ASIC_BASE+0x3000)
ARM7_EXTACON0   EQU  (ASIC_BASE+0x3008)
ARM7_EXTACON1   EQU  (ASIC_BASE+0x300c)
ARM7_EXTDBWTH   EQU  (ASIC_BASE+0x3010)
ARM7_ROMCON0   EQU  (ASIC_BASE+0x3014)
ARM7_ROMCON1   EQU  (ASIC_BASE+0x3018)
ARM7_ROMCON2   EQU  (ASIC_BASE+0x301c)
ARM7_ROMCON3   EQU  (ASIC_BASE+0x3020)
ARM7_ROMCON4   EQU  (ASIC_BASE+0x3024)
ARM7_ROMCON5   EQU  (ASIC_BASE+0x3028)
ARM7_DRAMCON0   EQU  (ASIC_BASE+0x302c)
ARM7_DRAMCON1   EQU  (ASIC_BASE+0x3030)
ARM7_DRAMCON2   EQU  (ASIC_BASE+0x3034)
ARM7_DRAMCON3   EQU  (ASIC_BASE+0x3038)
ARM7_REFEXTCON  EQU  (ASIC_BASE+0x303c)

; controller registers
ARM7_INTMODE  EQU  (ASIC_BASE+0x4000)
ARM7_INTPEND  EQU  (ASIC_BASE+0x4004)
ARM7_INTMASK  EQU  (ASIC_BASE+0x4008)
ARM7_INTOFFSET  EQU  (ASIC_BASE+0x4024)
ARM7_INTPENDTST EQU   (ASIC_BASE+0x402c)

ARM7_INTPRI0  EQU  (ASIC_BASE+0x400C)
ARM7_INTPRI1  EQU  (ASIC_BASE+0x4010)
ARM7_INTPRI2  EQU  (ASIC_BASE+0x4014)
ARM7_INTPRI3  EQU  (ASIC_BASE+0x4018)
ARM7_INTPRI4  EQU  (ASIC_BASE+0x401C)
ARM7_INTPRI5  EQU  (ASIC_BASE+0x4020)

ARM7_INTOSET_FIQ   EQU  (ASIC_BASE+0x4030)
ARM7_INTOSET_IRQ   EQU  (ASIC_BASE+0x4034)

; I/O Port Interface 
ARM7_IOPMOD   EQU  (ASIC_BASE+0x5000)
ARM7_IOPCON    EQU  (ASIC_BASE+0x5004)
ARM7_IOPDATA   EQU  (ASIC_BASE+0x5008)

; IIC Registers
ARM7_IICCON      EQU   (ASIC_BASE+0xf000)
ARM7_IICBUF      EQU   (ASIC_BASE+0xf004)
ARM7_IICPS       EQU  (ASIC_BASE+0xf008)
ARM7_IICCNT      EQU  (ASIC_BASE+0xf00c)

;/*************************************************************************/
;/*  SYSTEM MEMORY CONTROL REGISTER EQU TABLES                            */
;/*************************************************************************/

;***************Init***************
rEXTDBWTH  EQU  0x00003001
rROMCON0  EQU  0x02000060
rROMCON1    EQU   0x60
rROMCON2     EQU   0x60
rROMCON3     EQU   0x60
rROMCON4     EQU   0x60
rROMCON5     EQU   0x60
rSDRAMCON0    EQU   0x12008380
rSDRAMCON1    EQU   0x00
rSDRAMCON2    EQU   0x00
rSDRAMCON3    EQU   0x00
rSREFEXTCON  EQU  0xCE278360

;************Memory Remap**************
rEXTDBWTH_R  EQU  0x00003001
rROMCON0_R  EQU  0x12040060
rROMCON1_R   EQU   0x60
rROMCON2_R    EQU   0x60
rROMCON3_R    EQU   0x60
rROMCON4_R    EQU   0x60
rROMCON5_R    EQU   0x60
rSDRAMCON0_R    EQU   0x10000380
rSDRAMCON1_R    EQU   0x00
rSDRAMCON2_R    EQU   0x00
rSDRAMCON3_R    EQU   0x00
rSREFEXTCON_R EQU  0xCE278360

;/***************************************************************/
       END