RTL源文件：

/*This a 16 bits adder, use a clock*/

 

module adder16(cin,ain,bin,sout,cout,clk);

input clk;

input[15:0] ain,bin;

input cin;

output[15:0] sout;

output cout;

reg[15:0] sout;

reg cout;

reg[15:0] ain_temp,bin_temp;

reg cin_temp;

wire cout_temp;

wire[15:0] sout_temp;

 

always@(posedge clk)

begin

 ain_temp<=ain;

 bin_temp<=bin;

 cin_temp<=cin;

 sout<=sout_temp;

 cout<=cout_temp;

end

 

assign {cout_temp,sout_temp}=ain_temp+bin_temp+cin_temp;

 

endmodule

采用CSMC的库文件，综合脚本：

###############################################

#this script. is for adder16.v

#design by jovy

#2010-01-03

##############################################

set search_path [concat . /usr/synopsys/Z-2007.03-SP5/libraries/csmc06/lib]

set target_library csmc06core.db

set link_library [concat * csmc06core.db]

set symbol_library [concat csmc06core.sdb]

 

set technology "0.6 micro csmc"

set company "Tongji University"

set designer "Jovy"

 

set design_path "/usr/synopsys/dc_proj/Adder16/"

##################################################

#read the design source file

#############################################

analyze -format verilog "${design_path}adder16.v"

elaborate adder16

 

current_design adder16

#############################################

#define the design environment

#############################################

set_operating_conditions WORST

set_wire_load_model "0x150k"

set_drive 0 clk

set_driving_cell -lib_cell DFBTNB [all_inputs]

set_load 2.2 sout

set_load 1.5 cout

 

###############################################

#set the optimization constraints

##############################################

create_clock clk -period 12

set_input_delay 1.35 -clock clk -max {ain bin}

set_input_delay 1.5 -clock clk -max cin

#set_output_delay -max 1.4 -clock clk cout

set_dont_touch_network clk

set_max_area 0

#################################################

#map and optimize the design

#################################################

compile -map_effort high

###############################################

#analyze and debug the design

###############################################

report_constraints -all_violators > "${design_path}adder16.rpt"

report_area >> "${design_path}adder16.rpt"

##############################################

#save the design database

#############################################

write -format ddc -hierarchy -output "${design_path}adder16.ddc"

建立时间报告：

dc_shell-xg-t> report_timing

 

****************************************

Report : timing

        -path full

        -delay max

        -max_paths 1

Design : adder16

Version: Z-2007.03-SP5

Date   : Sat Jan  9 21:22:10 2010

****************************************

 

Operating Conditions: WORST   Library: csmc06core

Wire Load Model Mode: top

 

  Startpoint: bin_temp_reg[5]

              (rising edge-triggered flip-flop clocked by clk)

  Endpoint: sout_reg[15]

            (rising edge-triggered flip-flop clocked by clk)

  Path Group: clk

  Path Type: max

 

  Point                                                   Incr       Path

  --------------------------------------------------------------------------

  clock clk (rise edge)                                   0.00       0.00

  clock network delay (ideal)                             0.00       0.00

  bin_temp_reg[5]/CK (DFNTNB)                             0.00       0.00 r

  bin_temp_reg[5]/Q (DFNTNB)                              0.46       0.46 f

  add_1_root_add_25_2/B[5] (adder16_DW01_add_1)           0.00       0.46 f

  add_1_root_add_25_2/U37/Y (OR02D1)                      0.50       0.96 f

  add_1_root_add_25_2/U44/YN (IN01D1)                     0.25       1.21 r

  add_1_root_add_25_2/U43/YN (OA04D1)                     0.48       1.68 f

  add_1_root_add_25_2/U42/YN (IN01D3)                     0.25       1.93 r

  add_1_root_add_25_2/U41/YN (OA04D1)                     0.48       2.41 f

  add_1_root_add_25_2/U40/YN (AO04D1)                     1.00       3.41 r

  add_1_root_add_25_2/U39/YN (IN01D2)                     0.59       4.00 f

  add_1_root_add_25_2/U33/Y (OR02D1)                      0.74       4.73 f

  add_1_root_add_25_2/U51/YN (ND02D1)                     0.49       5.22 r

  add_1_root_add_25_2/U63/Y (AN03D1)                      0.78       6.01 r

  add_1_root_add_25_2/U59/YN (IN01D3)                     0.34       6.35 f

  add_1_root_add_25_2/U10/Y (NI01D2)                      0.44       6.79 f

  add_1_root_add_25_2/U132/YN (AO04D1)                    0.44       7.23 r

  add_1_root_add_25_2/U120/Y (OR02D1)                     0.61       7.84 r

  add_1_root_add_25_2/U91/Y (AN02D1)                      0.76       8.60 r

  add_1_root_add_25_2/U151/YN (OA04D1)                    0.92       9.52 f

  add_1_root_add_25_2/U150/Y (XO02D1)                     1.33      10.85 r

  add_1_root_add_25_2/U97/YN (IN01D3)                     0.58      11.43 f

  add_1_root_add_25_2/U98/YN (IN01D4)                     0.27      11.70 r

  add_1_root_add_25_2/SUM[15] (adder16_DW01_add_1)        0.00      11.70 r

  sout_reg[15]/D (DFNTNB)                                 0.00      11.70 r

  data arrival time                                                 11.70

 

  clock clk (rise edge)                                  12.00      12.00

  clock network delay (ideal)                             0.00      12.00

  sout_reg[15]/CK (DFNTNB)                                0.00      12.00 r

  library setup time                                     -0.18      11.82

  data required time                                                11.82

  --------------------------------------------------------------------------

  data required time                                                11.82

  data arrival time                                                -11.70

  --------------------------------------------------------------------------

  slack (MET)                                                        0.13

1

保持时间报告：

dc_shell-xg-t> report_timing -delay min

 

****************************************

Report : timing

        -path full

        -delay min

        -max_paths 1

Design : adder16

Version: Z-2007.03-SP5

Date   : Sat Jan  9 21:22:31 2010

****************************************

 

Operating Conditions: WORST   Library: csmc06core

Wire Load Model Mode: top

 

  Startpoint: cin_temp_reg

              (rising edge-triggered flip-flop clocked by clk)

  Endpoint: sout_reg[0]

            (rising edge-triggered flip-flop clocked by clk)

  Path Group: clk

  Path Type: min

 

  Point                                                   Incr       Path

  --------------------------------------------------------------------------

  clock clk (rise edge)                                   0.00       0.00

  clock network delay (ideal)                             0.00       0.00

  cin_temp_reg/CK (DFNTNB)                                0.00       0.00 r

  cin_temp_reg/QN (DFNTNB)                                0.43       0.43 f

  U37/YN (IN01D2)                                         0.15       0.58 r

  add_1_root_add_25_2/CI (adder16_DW01_add_1)             0.00       0.58 r

  add_1_root_add_25_2/U105/Y (XO02D1)                     0.15       0.74 f

  add_1_root_add_25_2/U106/YN (IN01D2)                    0.21       0.94 r

  add_1_root_add_25_2/SUM[0] (adder16_DW01_add_1)         0.00       0.94 r

  sout_reg[0]/D (DFNTNB)                                  0.00       0.94 r

  data arrival time                                                  0.94

 

  clock clk (rise edge)                                   0.00       0.00

  clock network delay (ideal)                             0.00       0.00

  sout_reg[0]/CK (DFNTNB)                                 0.00       0.00 r

  library hold time                                       0.00       0.00

  data required time                                                 0.00

  --------------------------------------------------------------------------

  data required time                                                 0.00

  data arrival time                                                 -0.94

  --------------------------------------------------------------------------

  slack (MET)                                                        0.94

 

 

1

dc_shell-xg-t> report_area

 

****************************************

Report : area

Design : adder16

Version: Z-2007.03-SP5

Date   : Sat Jan  9 21:23:15 2010

****************************************

 

Library(s) Used:

 

    csmc06core (File: /usr/synopsys/Z-2007.03-SP5/libraries/csmc06/lib/csmc06core.db)

 

Number of ports:               51

Number of nets:               136

Number of cells:               85

Number of references:           4

 

Combinational area:        952.000000

Noncombinational area:     650.000000

Net Interconnect area:      undefined  (No wire load specified)

 

Total cell area:          1602.000000

Total area:                 undefined

1

 

采用DC自带的库文件，综合脚本：

###############################################

#this script. is for adder16.v

#design by jovy

#2010-01-03

##############################################