日志
dc_shell教程
|
好长时间了想搞懂dc的脚本书写 终于让我找见一个好的教程 写的非常详细 弄过来给大家参考。
Design Compiler Tutorial
Before running synthesis the tool environment file must be sourced. If you have not done this please go back to the environment setup page. All steps on this page may be completed from a telnet or ssh window.
- Create a .synopsys_dc.setup environment file in your home directory specifying the location of the technology library files you want to use. Here is one premade that points to our open source technology libraries. Place a copy in your ~/ directory.
- Write the verilog code for the part you wish to synthesize. For the purposes of this example we will use the same verilog as the simulation tutorial:
module mux2_1 ( out, in0, in1, sel ) ; input [3:0] in0, in1; input sel; output [3:0] out; // All the real work gets done here in the assign. assign ut = sel ? in1 : in0; endmodule // mux2_1
As you can see this is a very simple four bit 2 to 1 mux. You may also copy the file from here . - Next one must write a design complier script. The script. should do the following:
- Load all the verilog files into dc_shell and tell dc_shell which module is the top level module.
- Set up the constraints for compilation. The contraints tune how the dc_shell tool converts the behavioral RTL into a netlist. For example one may set timing contraints or area contraints dependent on which is more important for the design at hand.
- Issue the compile command and tell dc_shell to report back on the resultant area and timing so the designer will get feedback on the resultant design.
- Save the netlist back to a verilog format for use in downstream tools.
Here is an example design compiler shell script. for the mux2_1 that does all of these things:# Load up the verilog files (when more files are included there # will be more analyze lines) analyze -format verilog ./mux2_1.v # Tell dc_shell the name of the top level module elaborate mux2_1 # Set timing constaints, this says that a max of .5ns of delay from # input to output is alowable set_max_delay .5 -to [all_outputs] # Set the characteristics of the driving cell for all inputs set_driving_cell -lib_cell INVX1 -pin Y [all_inputs] # If this were a clocked piece of logic we could set a clock # period to shoot for like this # create_clock clk -period 1.800 # Check for warnings/errors check_design # Use module compiler for arth. DW components set dw_prefer_mc_inside true # ungroup everything ungroup -flatten -all # flatten it all, this forces all the hierarchy to be flattened out set_flatten true -effort high uniquify # This forces the compiler to spend as much effort (and time) # compiling this RTL to achieve timing possible. compile_ultra # Now that the compile is complete report on the results report_area report_timing # Finally write the post synthesis netlist out to a verilog file write -f verilog mux2_1 -output mux2_1_post_synth.v -hierarchy exit
A copy of this may be downloaded from here . - Now everything is set to compile the mux. Do do so issue the command shown in red in the directory containing the files listed above.
pgratz@desk workingdir $ dc_shell-t -f mux2_1.dc_cmd | tee output.txt
- Assuming no errors occur there will be several new files in your directory once dc_shell is done. The first one to look at is the output.txt file. This is the log of the compile output. Looking at this copy for comparison you should look over the warnings and errors and determine if there were any problems durning compile. Note: some warnings are not indicative of a problem with your design. If the warning appears in the sample output.txt then it can safely be ignored.
- Once satisfied that there are no errors in the run you should skim down nearly to the bottom of output.txt where you will find some text like the following:
... report_area Information: Updating design information... (UID-85) **************************************** Report : area Design : mux2_1 Version: V-2004.06-SP1 Date : Mon Nov 27 00:54:53 2006 **************************************** Library(s) Used: osu018_stdcells (File: /projects/cad/open_source_synth_libs/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.db) Number of ports: 13 Number of nets: 17 Number of cells: 8 Number of references: 2 Combinational area: 256.000000 Noncombinational area: 0.000000 Net Interconnect area: undefined (No wire load specified) Total cell area: 256.000000 Total area: undefined 1 ...This is the area report from the synthesis run. The important data here is the "Total cell area: 256.000000". This states that the total area used by the design is 256 "cell units". - Skimming further down in output.txt you will find the following output:
... report_timing **************************************** Report : timing -path full -delay max -max_paths 1 Design : mux2_1 Version: V-2004.06-SP1 Date : Mon Nov 27 00:54:53 2006 **************************************** Operating Conditions: typical Library: osu018_stdcells Wire Load Model Mode: top Startpoint: sel (input port) Endpoint: out[0] (output port) Path Group: default Path Type: max Point Incr Path ----------------------------------------------------------- input external delay 0.00 0.00 r sel (in) 0.13 0.13 r U20/Y (MUX2X1) 0.15 0.28 f U19/Y (INVX2) 0.03 0.31 r out[0] (out) 0.00 0.31 r data arrival time 0.31 max_delay 0.50 0.50 output external delay 0.00 0.50 data required time 0.50 ----------------------------------------------------------- data required time 0.50 data arrival time -0.31 ----------------------------------------------------------- slack (MET) 0.19 1 ...This piece of text is the output of the timing report. It details the worst case or slowest path through the post synthesis design. Times are shown in pico seconds. In this case it shows that the slowest path through the design takes .31ns. In the mux2_1.dc_cmd file we placed a constraint on the timing that all outputs must be asserted by at least .500 ns after the inputs change and this is shown in the "data required time". The "slack" is the difference between the worst case path and the required time. In this case timing is met so the slack is a positive .19 ps. If timing was not met then the slack would be a negative value. - Another file created during the synthesis step above is the "mux2_1_post_synth.v" file. The contents of this file should be like this:
module mux2_1 ( out, in0, in1, sel ); output [3:0] out; input [3:0] in0; input [3:0] in1; input sel; wire n7, n8, n9, n10; INVX2 U13 ( .A(n7), .Y(out[3]) ); MUX2X1 U14 ( .A(in1[3]), .B(in0[3]), .S(sel), .Y(n7) ); INVX2 U15 ( .A(n8), .Y(out[2]) ); MUX2X1 U16 ( .A(in1[2]), .B(in0[2]), .S(sel), .Y(n8) ); INVX2 U17 ( .A(n9), .Y(out[1]) ); MUX2X1 U18 ( .A(in1[1]), .B(in0[1]), .S(sel), .Y(n9) ); INVX2 U19 ( .A(n10), .Y(out[0]) ); MUX2X1 U20 ( .A(in1[0]), .B(in0[0]), .S(sel), .Y(n10) ); endmodule
As you can see this is the post synthesis netlist written out durning the final step in the mux2_1.dc_cmd. In it the behavioral "assign" statment has been replaced with multiple instatiations of single bit library MUX2X1 mux cells and some INVX2 inverter cells.
This completes the design compiler tutorial. More information on design compiler may be found on the main cad page under synthesis documentation.
Modified by Paul Gratz, pgratz@cs.utexas.edu
.synopsys_dc.setup
set search_path [list "." "/projects/cad/open_source_synth_libs/osu_stdcells/lib/tsmc018/lib" "/projects/cad/synopsys/synth/libraries/syn/" "/projects/cad/synopsys/synth/mc/lib/dp/dplite/" "/projects/cad/synopsys/synth/mc/lib/dp" "/projects/cad/synopsys/synth/dw/sim_ver/"] set target_library [list osu018_stdcells.db] set synthetic_library [list dw_foundation.sldb dw01.sldb dw02.sldb dw03.sldb dw04.sldb dw05.sldb dw06.sldb dw08.sldb dw07.sldb standard.sldb] set link_library [concat $target_library $synthetic_library] set command_log_file "./command.log" define_design_lib WORK -path ./work
脚本文件
# Load up the verilog files (when more files are included there # will be more analyze lines) analyze -format verilog ./mux2_1.v # Tell dc_shell the name of the top level module elaborate mux2_1 # Set timing constaints, this says that a max of .5ns of delay from # input to output is alowable set_max_delay .5 -to [all_outputs] # Set the characteristics of the driving cell for all inputs set_driving_cell -lib_cell INVX1 -pin Y [all_inputs] # If this were a clocked piece of logic we could set a clock # period to shoot for like this # create_clock clk -period 1.800 # Check for warnings/errors check_design # Use module compiler for arth. DW components set dw_prefer_mc_inside true # ungroup everything ungroup -flatten -all # flatten it all, this forces all the hierarchy to be flattened out set_flatten true -effort high uniquify # This forces the compiler to spend as much effort (and time) # compiling this RTL to achieve timing possible. compile_ultra # Now that the compile is complete report on the results report_area report_timing # Finally write the post synthesis netlist out to a verilog file write -f verilog mux2_1 -output mux2_1_post_synth.v -hierarchy exit写好以后在在当前目录里面运行 dc_shell-t -f mux2_1.dc_cmd |tee output.txt就可以了结果一般如下：：DC Professional (TM) DC Expert (TM) DC Ultra (TM) Vhdl Compiler (TM) HDL Compiler (TM) Library Compiler (TM) Power Compiler (TM) DFT Compiler (TM) BSD Compiler DesignWare Developer (TM) Version V-2004.06-SP1 for linux -- Jul 15, 2004 Copyright (c) 1988-2004 by Synopsys, Inc. ALL RIGHTS RESERVED This program is proprietary and confidential information of Synopsys, Inc. and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure. Initializing... # Load up the verilog files (when more files are included there # will be more analyze lines) analyze -format verilog ./mux2_1.v Running PRESTO HDLC Compiling source file ./mux2_1.v Presto compilation completed successfully. 1 # Tell dc_shell the name of the top level module elaborate mux2_1 Running PRESTO HDLC Loading db file '/projects/cad/synopsys/synth/libraries/syn/gtech.db' Loading db file '/projects/cad/synopsys/synth/libraries/syn/standard.sldb' Loading db file '/projects/cad/synopsys/synth/libraries/syn/dw_foundation.sldb' Loading db file '/projects/cad/synopsys/synth/libraries/syn/dw01.sldb' Loading db file '/projects/cad/synopsys/synth/libraries/syn/dw02.sldb' Loading db file '/projects/cad/synopsys/synth/libraries/syn/dw03.sldb' Loading db file '/projects/cad/synopsys/synth/libraries/syn/dw04.sldb' Loading db file '/projects/cad/synopsys/synth/libraries/syn/dw05.sldb' Loading db file '/projects/cad/synopsys/synth/libraries/syn/dw06.sldb' Loading db file '/projects/cad/synopsys/synth/libraries/syn/dw08.sldb' Loading db file '/projects/cad/synopsys/synth/libraries/syn/dw07.sldb' Loading db file '/projects/cad/open_source_synth_libs/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.db' Presto compilation completed successfully. Current design is now 'mux2_1' 1 # Set timing constaints, this says that a max of .5ns of delay from # input to output is alowable set_max_delay .5 -to [all_outputs] 1 # Set the characteristics of the driving cell for all inputs set_driving_cell -lib_cell INVX1 -pin Y [all_inputs] Warning: Design rule attributes from the driving cell will be set on the port. (UID-401) 1 # If this were a clocked piece of logic we could set a clock # period to shoot for like this # create_clock clk -period 1.800 # Check for warnings/errors check_design 1 # Use module compiler for arth. DW components set dw_prefer_mc_inside true true # ungroup everything ungroup -flatten -all Current instance is the top-level of design 'mux2_1'. Information: Updating design information... (UID-85) Warning: Design has no hierarchy. No cells can be ungrouped. (UID-228) 0 # flatten it all, this forces all the hierarchy to be flattened out set_flatten true -effort high 1 uniquify 1 # This forces the compiler to spend as much effort (and time) # compiling this RTL to achieve timing possible. compile_ultra Information: Data-path optimization is enabled. (DP-1) Information: Evaluating DesignWare library utilization. (UISN-27) ============================================================================ | DesignWare Building Block Library | Version | Available | ============================================================================ | Basic DW Building Blocks | V-2004.06-DWF_0406 | * | | Licensed DW Building Blocks | V-2004.06-DWF_0406 | * | ============================================================================ Beginning Pass 1 Mapping ------------------------ Processing 'mux2_1' Updating timing information Beginning Mapping Optimizations (Ultra High effort) ------------------------------- Information: There is no timing violation in design mux2_1. Delay-based auto_ungroup will not be performed. (OPT-780) Flattening 'mux2_1' (High effort) (Single Output Minimization) Structuring 'mux2_1' Mapping 'mux2_1' ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- 0:00:00 256.0 0.00 0.0 0.0 0:00:00 256.0 0.00 0.0 0.0 Beginning Delay Optimization Phase ---------------------------------- ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- 0:00:00 256.0 0.00 0.0 0.0 0:00:00 256.0 0.00 0.0 0.0 0:00:00 256.0 0.00 0.0 0.0 Beginning Mapping Optimizations (Ultra High effort) (Incremental) ------------------------------- Beginning Delay Optimization Phase ---------------------------------- ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- 0:00:00 256.0 0.00 0.0 0.0 Beginning Area-Recovery Phase (max_area 0) ----------------------------- ELAPSED WORST NEG TOTAL NEG DESIGN TIME AREA SLACK SLACK RULE COST ENDPOINT --------- --------- --------- --------- --------- ------------------------- 0:00:00 256.0 0.00 0.0 0.0 0:00:00 256.0 0.00 0.0 0.0 0:00:00 256.0 0.00 0.0 0.0 0:00:00 256.0 0.00 0.0 0.0 0:00:00 256.0 0.00 0.0 0.0 0:00:00 256.0 0.00 0.0 0.0 Optimization Complete --------------------- Transferring design 'mux2_1' to database 'mux2_1.db' Current design is 'mux2_1'. 1 # Now that the compile is complete report on the results report_area Information: Updating design information... (UID-85) **************************************** Report : area Design : mux2_1 Version: V-2004.06-SP1 Date : Mon Nov 27 00:54:53 2006 **************************************** Library(s) Used: osu018_stdcells (File: /projects/cad/open_source_synth_libs/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.db) Number of ports: 13 Number of nets: 17 Number of cells: 8 Number of references: 2 Combinational area: 256.000000 Noncombinational area: 0.000000 Net Interconnect area: undefined (No wire load specified) Total cell area: 256.000000 Total area: undefined 1 report_timing **************************************** Report : timing -path full -delay max -max_paths 1 Design : mux2_1 Version: V-2004.06-SP1 Date : Mon Nov 27 00:54:53 2006 **************************************** Operating Conditions: typical Library: osu018_stdcells Wire Load Model Mode: top Startpoint: sel (input port) Endpoint: out[0] (output port) Path Group: default Path Type: max Point Incr Path ----------------------------------------------------------- input external delay 0.00 0.00 r sel (in) 0.13 0.13 r U20/Y (MUX2X1) 0.15 0.28 f U19/Y (INVX2) 0.03 0.31 r out[0] (out) 0.00 0.31 r data arrival time 0.31 max_delay 0.50 0.50 output external delay 0.00 0.50 data required time 0.50 ----------------------------------------------------------- data required time 0.50 data arrival time -0.31 ----------------------------------------------------------- slack (MET) 0.19 1 # Finally write the post synthesis netlist out to a verilog file write -f verilog mux2_1 -output mux2_1_post_synth.v -hierarchy 1 exitInformation: Defining new variable 'synlib_iis_accept_all_gened_impl'. (CMD-041) Thank you...基本就可以了 成功后可以分析一下代码写的过程 基本就可以搞懂怎么实现脚本的书写了要注意的有两点首先要修改设置里面的目录。其次是脚本语言的后缀要写对这样在没有问题执行以后
/2 
eetop公众号
创芯大讲堂
创芯人才网