Abstract(摘要)

FIFOs are often used to safely pass data from one clock domain to another asynchronous clock domain. Using a
FIFO to pass data from one clock domain to another clock domain requires multi-asynchronous clock design
techniques. There are many ways to design a FIFO wrong. There are many ways to design a FIFO right but still
make it difficult to properly synthesize and analyze the design.

FIFO通常用于安全地从一个时钟域向另一个时钟域传递数据。利用FIFO从一个时钟域向另一个时钟域传递数据需要利用跨时钟设计技术。设计FIFO的方法有很多，但是很多设计方法会使FIFO的综合和分析变得异常苦难。

This paper will detail one method that is used to design, synthesize and analyze a safe FIFO between different clock domains using Gray code pointers that are synchronized into a different clock domain before testing for "FIFO full"
or "FIFO empty" conditions. The fully coded, synthesized and analyzed RTL Verilog model (FIFO Style. #1) is
included.

本文将详细介绍一种FIFO的设计、综合以及分析方法，该方法使用Gray码指针，在测试FIFO满或者空时，首先将Gray码指针同步到发送或者接受时钟域。论文最后给出了该FIFO设计的可综合的RTL级全部代码。

1.0 引言(Introduction)

An asynchronous FIFO refers to a FIFO design where data values are written to a FIFO buffer from one clock
domain and the data values are read from the same FIFO buffer from another clock domain, where the two clock
domains are asynchronous to each other.

FIFO指的是一种具有先进先出机制的存储缓冲器，异步FIFO指的是对FIFO的读操作和写操作在不同时钟域进行，也就是说读操作和写操作在两个不同的异步时钟域中进行。

Asynchronous FIFOs are used to safely pass data from one clock domain to another clock domain。

异步FIFO通常被用于从一个时钟域向另一个时钟域中传递数据，通常是对数据传递安全性要求较高的场合。

There are many ways to do asynchronous FIFO design, including many wrong ways. Most incorrectly implemented FIFO designs still function properly 90% of the time. Most almost-correct FIFO designs function properly 99%+ of the time. Unfortunately, FIFOs that work properly 99%+ of the time have design flaws that are usually the most difficult to detect and debug (if you are lucky enough to notice the bug before shipping the product), or the most costly to diagnose and recall (if the bug is not discovered until the product is in the hands of a dissatisfied customer).

设计异步FIFO的方法有很多，当然有很多的方法是不对的。尽管这些FIFO设计不正确，但是它们可能在90%的时间都能保持正确工作，甚至队友有些FIFO，虽然它们设计上仍然不完全正确，但他们可能在99%的时间内都能保证正确工作。不幸的是，这些99%时间都能正确工作的FIFO在设计上的瑕疵通常情况下是最难发现和调试的，而且发现这些瑕疵的成本可能也是最高的。

本文将讨论一种FIFO的设计方法以及该方法的一些重要细节，这些细节都是FIFO设计过程中必须要考虑的。