The Programmable Interrupt Controller (PIC) functions as an overall manager in an Interrupt-Driven system environment. It accepts requests from the peripheral equipment, determines which of the incoming
requests is of the highest importance (priority),ascertains whether the incoming request has a higher priority value than the level currently being serviced, and issues an interrupt to the CPU based on this determination.

  Each peripheral device or structure usually has a special program or ``routine'' that is associated with its specific functional or operational requirements; this is referred to as a ``service routine''. The PIC, after issuing an Interrupt to the CPU, must somehow input information into the CPU that can ``point'' the Program Counter to the service routine associated with the requesting device. This ``pointer'' is an address
in a vectoring table and will often be referred to, in this document, as vectoring data.

INTERRUPT REQUEST REGISTER (IRR) AND IN-SERVICE REGISTER (ISR)
  The interrupts at the IR input lines are handled by two registers in cascade, the Interrupt Request Register(IRR) and the In-Service (ISR). The IRR is used to store all the interrupt levels which are requesting
service; and the ISR is used to store all the interrupt levels which are being serviced.

PRIORITY RESOLVER
This logic block determines the priorites of the bits
set in the IRR. The highest priority is selected and
strobed into the corresponding bit of the ISR during
INTA pulse.

(Priority resolver记录了IRR中的中断优先级，最高优先级的中断将会在INTA脉冲到来期间相应地设置ISR)

INTERRUPT MASK REGISTER (IMR)
The IMR stores the bits which mask the interrupt
lines to be masked. The IMR operates on the IRR.
Masking of a higher priority input will not affect the
interrupt request lines of lower quality.

READ/WRITE CONTROL LOGIC
The function of this block is to accept OUTput commands from the CPU. It contains the Initialization Command Word (ICW) registers and Operation
Command Word (OCW) registers which store the various control formats for device operation. This function block also allows the status of the 8259A to be transferred onto the Data Bus.

THE CASCADE BUFFER/COMPARATOR
This function block stores and compares the IDs of all 8259A's used in the system. The associated three I/O pins (CAS0-2) are outputs when the 8259A is used as a master and are inputs when the 8259A is used as a slave. As a master, the 8259A sends the ID of the interrupting slave device onto the CAS0-2 lines. The slave thus selected will send its
preprogrammed subroutine address onto the Data Bus during the next one or two consecutive INTA pulses. (See section ``Cascading the 8259A''.)

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The normal sequence of events during an interrupt in an 8086 system:
1. One or more of the INTERRUPT REQUEST lines (IR7-0) are raised high, setting the corresponding IRR bit(s).

(IR7-0有中断请求，此时相应的IRR位置位)

2. The 8259A evaluates these requests, and sends an INT to the CPU, if appropriate.

(然后8259发送INT信号给8086)

3. The CPU acknowledges the INT and responds with an INTA pulse.

(8086受到INT后，发送响应信号INTA)

4. Upon receiving an INTA from the CPU group, the highest priority ISR bit is set and the corresponding IRR bit is reset. The 8259A does not drive the Data Bus during this cycle.

(8259受到INTA响应后，设置具有最高优先级的中断，ISR中相应位置位，并且IRR该位清零)

5. The 8086 will initiate a second INTA pulse. During this pulse, the 8259A releases an 8-bit pointer onto the Data Bus where it is read by the CPU.

(然后8086发送第二个INTA信号，在该脉冲到来期间，8259发送8位中断向量到数据总线)

6. This completes the interrupt cycle. In the AEOI mode the ISR bit is reset at the end of the second INTA pulse. Otherwise, the ISR bit remains
set until an appropriate EOI command is issued at the end of the interrupt subroutine.

(最后，如果是AEOI模式，在第二个INTA脉冲结束后，刚才置位的ISR位清零，如果不在AEOI模式，需要发送EOI指令清零ISR位)

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  If no interrupt request is present at step 4 of either sequence (i.e., the request was too short in duration) the 8259A will issue an interrupt level 7. Both the vectoring bytes and the CAS lines will look like an interrupt level 7 was requested.

  When the 8259A PIC receives an interrupt, INT becomes active and an interrupt acknowledge cycle is started. If a higher priority interrupt occurs between the two INTA pulses, the INT line goes inactive immediately after the second INTA pulse. After an unspecified
amount of time the INT line is activated again to signify the higher priority interrupt waiting for service. This inactive time is not specified and
can vary between parts. The designer should be aware of this consideration when designing a system which uses the 8259A. It is recommended that proper asynchronous design techniques be followed.

(当8259受到一个中断信号后，INT开始有效，也预示着中断响应周期的开始，如果此时一个更高优先级的中断在两个INTA之间出现，那么INT线会在第二个INTA结束后失效一段不能预计的时间，当过了这段时间后，INT重新有效，注：这段时间可能变化！！！)

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Content of Interrupt Vector Byte
for 8086 System Mode
     D7 D6 D5 D4 D3      D2 D1 D0
IR7 T7 T6 T5 T4 T3         1    1    1
IR6 T7 T6 T5 T4 T3         1    1    0
IR5 T7 T6 T5 T4 T3         1    0    1
IR4 T7 T6 T5 T4 T3         1    0    0
IR3 T7 T6 T5 T4 T3         0    1    1
IR2 T7 T6 T5 T4 T3         0    1    0
IR1 T7 T6 T5 T4 T3         0    0    1
IR0 T7 T6 T5 T4 T3         0    0    0

PROGRAMMING THE 8259A
The 8259A accepts two types of command words generated by the CPU:
1. Initialization Command Words (ICWs): Before normal operation can begin, each 8259A in the system must be brought to a starting point-by a sequence of 2 to 4 bytes timed by WR pulses.
2. Operation Command Words (OCWs): These are the command words which command the 8259A to operate in various interrupt modes. These
modes are:
a. Fully nested mode
b. Rotating priority mode
c. Special mask mode
d. Polled mode
The OCWs can be written into the 8259A anytime after initialization.

Operation Control Words (OCWs)
OCW1
A0 D7 D6 D5 D4 D3 D2 D1 D0
1 M7 M6 M5 M4 M3 M2 M1 M0
OCW2
0 R SL EOI 0 0 L2 L1 L0
OCW3
0 0 ESMM SMM 0 1 P RR RIS

未完待续...