0413

Beginning of ICC2 (lab1 floorplanning)

1 insert block

 A block refers to a container of design data using “read_verilog”to create a block.

Related Command: open_block save_block

Open an existing block: open_block XX.dlib(nlib):XX/floorplan

2 Initial floorplan

Task Assistant (rightside palatte):Select Design Planning——Floorplan Preparation——Floorplan initialization——Type(Rec/L…)、Orientation（N、W、S、E）、Size Control、Spacing Value——Preview then Apply

TCL Command: initialize_floorplan -core_utilization 0.7 -shape L -orientation W \ -size_ratio {2 2 1 2} -core_offset {20} -flip_first_row true -coincident_boundary true

3 Block Shaping

Task Assistant: Block Shaping——shape blocks——apply

TCL Command:shape blocks

4 Macro and Standard Cell Placement

Tasks:Cell Placement——Cell Placement——Floorplanning Placement——Apply、

TCL Command:Create_Placement -effort medium -floorplan

5 Place Block Ports

To set pins around block area,meanwhile limit metal layer of these pins:

set_block_pin_constraints -self -allowed_layers {M3 M4 M5 M6}

place_pins -self

Create pin guide(highlight certain ports) to constraint specified pins(clk) to be placed in certain area:

change_selection [get_ports *clk]

# Press ctrl-t or use the following Tcl command:

gui_zoom -window [gui_get_current_window -view] -selection

change width or length of clk ports then rerun placement

set_individual_pin_constraints -ports [get_ports *clk] -length 0.1

place_pins -self

6 Congestion Map

Congestion: Available routing resources are less than planning routing resources, which may lead to mass of anti design rule case.

Congestion map——Global Route Congestion(GRC)——Reload

7 Data Flow Flylines & Tracing

To check connections between gates and registers

Data Flow Flylines——Reload

To check flylines between macro and registers

Register Tracing——reload——End points & Direct end points

TCL Command: set_placement_status fixed [get_cells -hierarchical -filter "is_hard_macro"]

8 PG Prototyping

Initialize PG mesh in a quick way.

Tasks——PG Planning——PG Prototyping——Specify Metal layer （Vertical and Horizontal）——Apply

9 Power Network Synthesis

Source scripts/pns.tcl

10 save lib