import pandas as pd

import time

local_time = time.strftime("//        %Y-%m-%d %H:%M:%S", time.localtime())

excel = "XXX.xlsx"

sheet = 0

output = "XXX.v"

# Columns A–D = index 0–3:

COL_ADDR = 0

COL_NAME = 1

COL_RESET = 2

COL_LATCH = 3

def is_dual_latch(x):

    if (x=='aev'):

        return True

    else:

        return False

def is_zero(x):

    if (x==0):

        return True

    else:

        return False

df = pd.read_excel(excel, sheet_name=sheet)

df_filtered = df.iloc[3:][df.iloc[3:,COL_NAME] != 0][df.iloc[3:,COL_NAME].notna()].copy()

reg_defs = []

reg_lat = []

lat_blocks = []

dff_blocks = []

dff2_blocks = []

assign_lines = []

readcase_lines = []

reg_table = []

# ------------------------------------------------------------

# PROCESS EACH REGISTER

# ------------------------------------------------------------

for _, row in df_filtered.iterrows():

    name = str(row[COL_NAME]).strip()

    addr = int(row[COL_ADDR])

    rstv = str(row[COL_RESET]).strip()

    aev  = str(row[COL_LATCH]).strip()

    #rstv = int(row[COL_RESET], 16) if isinstance(row[COL_RESET], str) else int(row[COL_RESET])

    dual = is_dual_latch(row[COL_LATCH])

    if dual:

        reg_table.append(f"{addr} {name} {rstv} {aev}")

    else:

        reg_table.append(f"{addr} {name} {rstv}")

    dff = f"dff_{addr}"

    defi = f"def_{addr}"

    lat = f"lat_{addr}"

    # output port name

    port = f"{name}"

    # --------------------------------------------

    # Declarations (same as your file)

    # --------------------------------------------

    reg_defs.append(f" reg [15:0] {dff} ; wire [15:0] {defi} = {rstv} ; /// {port}")

    if dual:

        reg_lat.append(f" reg [15:0] {lat} ;")

    # --------------------------------------------

    # Dual latch stage (lat_x)

    # --------------------------------------------

    if dual:

        # second stage

    # --------------------------------------------

    # Normal single-stage register

    # --------------------------------------------

    else:

        dff_blocks.append(f" always @(posedge sclk , negedge rstb_async) begin")

        dff_blocks.append(f"   if (!rstb_async) {dff} <= {defi};")

        dff_blocks.append(f"   else if (addr == 7'd{addr} && !wen) {dff} <= wdata;")

        dff_blocks.append(f" end\n")

    # --------------------------------------------

    # Output assign and read-case

    # --------------------------------------------

    assign_lines.append(f"  assign  {port} = {dff};")

    readcase_lines.append(f"       7'd{addr}: rdata = {dff};")

reg_ports[-1] = reg_ports[-1].rstrip(',')

# ------------------------------------------------------------

# BUILD FILE CONTENT

# ------------------------------------------------------------

out = []

out.append("//////////////////////////////////////")

out.append(local_time)

out.append("//////////////////////////////////////")

out.append("// define initial value //////////\n")

out.extend(reg_lat)

out.extend(reg_defs)

out.append("\n//////////////////////////////////")

out.append("// lat define ////////////////////\n")

out.extend(lat_blocks)

out.append("//////////////////////////////////")

out.append("// dff define ////////////////////\n")

out.append("// 2nd stage define //////////////\n")

out.extend(dff2_blocks)

out.append("//////////////////////////////////\n")

out.extend(dff_blocks)

out.append("//////////////////////////////////")

out.append("// create bus ////////////////////\n")

out.extend(assign_lines)

out.append("")

out.append("//////////////////////////////////")

out.append("// abus read /////////////////////\n")

out.append("  always @(*) begin")

out.append("    case (addr)")

out.extend(readcase_lines)

out.append("       default: rdata = 0;")

out.append("    endcase")

out.append("  end\n")

with open(output, "w") as f:

    f.write("\n".join(out))

print("Generated:", output)