日志
formality check
| ||
set hdlin_unresolved_modules black_box
library_verification verilog_db
set verificatin_passing_mode equality
set_app_var verification_inversion_push true
read_verilog -r -technology_library xxx.v
read_db -i -technology_library xxx.db
report_cell_list -verify
report_cell_list -matched
report_cell_list -unmatched
verify
report_status -pass
report_status -fail
report_status -abort
exit
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