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scramble for PCIe(Gen3/gen4)

已有 7 次阅读| 2023-7-20 18:05 |个人分类:数据处理|系统分类:芯片设计| scramble, PCIE
`timescale 1ns/1ps

module scramble_128(
                    //input 
                    input          clk        ,              //system clock
                    input          rst_b       ,              //reset signal
                    input [7:0]       dain       ,              //data input
                    input          bypass_scr    ,              //bypass scrambing when Elextrical Idle Exit Ordered set
                    input          K         ,              // K symbol
                    
                    output reg [7:0]    scr_da                    //scramble data out
                    );



reg [22:0]         LFSR             ;
wire[22:0]          LFSR_N            ;
wire[7:0]          data_nxt           ;

wire[22:0]                 LFSR_tmp_0 , 
                  LFSR_tmp_1 ,
                  LFSR_tmp_2 ,
                  LFSR_tmp_3 ,
                  LFSR_tmp_4 ,
                  LFSR_tmp_5 ,
                  LFSR_tmp_6 ,
                  LFSR_tmp_7 ;

wire              EIEOS_ind ;


parameter         DB = 2'b01          ;                   //data block header
parameter         OB = 2'b10          ;                   //ordered block header

parameter         SEED = 23'h1DBFBC   ;                   // for lane 0

parameter         EIEOS = 8'hFC       ;                   //need to check EIEOS symbol in 128b/130b


assign           EIEOS_ind = (dain == EIEOS) & K ;

always @(posedge clk or negedge rst_b)
  begin
   if(!rst_b)
    LFSR  <= #1 SEED     ;
   else if(EIEOS_ind)
    LFSR <= #1 SEED      ;
   else
    LFSR  <= #1 LFSR_N   ;
  end


always @(posedge clk or negedge rst_b)
  begin
   if(!rst_b)
    scr_da <= #1 8'h0   ;
   else if(bypass_scr)
    scr_da <= #1 dain ;
   else if(EIEOS_ind)
    scr_da <= #1 dain ;
   else
    scr_da <= #1 data_nxt ;
  end

LFSR_SHIFT I_LFSR_SHIFT_0 (.LFSR_cur (LFSR),    .datain(dain[0]), .LFSR_next(LFSR_tmp_1), .dataout(data_nxt[0]));
LFSR_SHIFT I_LFSR_SHIFT_1 (.LFSR_cur (LFSR_tmp_1), .datain(dain[1]), .LFSR_next(LFSR_tmp_2), .dataout(data_nxt[1]));
LFSR_SHIFT I_LFSR_SHIFT_2 (.LFSR_cur (LFSR_tmp_2), .datain(dain[2]), .LFSR_next(LFSR_tmp_3), .dataout(data_nxt[2]));
LFSR_SHIFT I_LFSR_SHIFT_3 (.LFSR_cur (LFSR_tmp_3), .datain(dain[3]), .LFSR_next(LFSR_tmp_4), .dataout(data_nxt[3]));
LFSR_SHIFT I_LFSR_SHIFT_4 (.LFSR_cur (LFSR_tmp_4), .datain(dain[4]), .LFSR_next(LFSR_tmp_5), .dataout(data_nxt[4]));
LFSR_SHIFT I_LFSR_SHIFT_5 (.LFSR_cur (LFSR_tmp_5), .datain(dain[5]), .LFSR_next(LFSR_tmp_6), .dataout(data_nxt[5]));
LFSR_SHIFT I_LFSR_SHIFT_6 (.LFSR_cur (LFSR_tmp_6), .datain(dain[6]), .LFSR_next(LFSR_tmp_7), .dataout(data_nxt[6]));
LFSR_SHIFT I_LFSR_SHIFT_7 (.LFSR_cur (LFSR_tmp_7), .datain(dain[7]), .LFSR_next(LFSR_N),     .dataout(data_nxt[7]));


reg [22:0] LFSR_tmp ;
wire[22:0] LFSR_N_tmp;

always @(posedge clk or negedge rst_b)
  begin
   if(!rst_b)
    LFSR_tmp  <= #1 SEED     ;
   else
    LFSR_tmp  <= #1 LFSR_N_tmp   ;
  end

assign LFSR_N_tmp[22] = LFSR_tmp[14] ^ LFSR_tmp[16] ^ LFSR_tmp[18] ^ LFSR_tmp[20] ^ LFSR_tmp[21] ^ LFSR_tmp[22] ;
assign LFSR_N_tmp[21] = LFSR_tmp[13] ^ LFSR_tmp[15] ^ LFSR_tmp[17] ^ LFSR_tmp[19] ^ LFSR_tmp[20] ^ LFSR_tmp[21] ;
assign LFSR_N_tmp[20] = LFSR_tmp[12] ^ LFSR_tmp[19] ^ LFSR_tmp[21] ;
assign LFSR_N_tmp[19] = LFSR_tmp[11] ^ LFSR_tmp[18] ^ LFSR_tmp[20] ^ LFSR_tmp[22] ;
assign LFSR_N_tmp[18] = LFSR_tmp[10] ^ LFSR_tmp[17] ^ LFSR_tmp[19] ^ LFSR_tmp[21] ;
assign LFSR_N_tmp[17] = LFSR_tmp[9] ^ LFSR_tmp[16] ^ LFSR_tmp[18] ^ LFSR_tmp[20] ^ LFSR_tmp[22] ;
assign LFSR_N_tmp[16] = LFSR_tmp[8] ^ LFSR_tmp[15] ^ LFSR_tmp[17] ^ LFSR_tmp[19] ^ LFSR_tmp[21] ^ LFSR_tmp[22] ;
assign LFSR_N_tmp[15] = LFSR_tmp[7] ^ LFSR_tmp[22] ;
assign LFSR_N_tmp[14] = LFSR_tmp[6] ^ LFSR_tmp[21] ;
assign LFSR_N_tmp[13] = LFSR_tmp[5] ^ LFSR_tmp[20] ^ LFSR_tmp[22] ;
assign LFSR_N_tmp[12] = LFSR_tmp[4] ^ LFSR_tmp[19] ^ LFSR_tmp[21] ^ LFSR_tmp[22] ;
assign LFSR_N_tmp[11] = LFSR_tmp[3] ^ LFSR_tmp[18] ^ LFSR_tmp[20] ^ LFSR_tmp[21] ^ LFSR_tmp[22] ;
assign LFSR_N_tmp[10] = LFSR_tmp[2] ^ LFSR_tmp[17] ^ LFSR_tmp[19] ^ LFSR_tmp[20] ^ LFSR_tmp[21] ^ LFSR_tmp[22] ;
assign LFSR_N_tmp[9]  = LFSR_tmp[1] ^ LFSR_tmp[16] ^ LFSR_tmp[18] ^ LFSR_tmp[19] ^ LFSR_tmp[20] ^ LFSR_tmp[21] ;
assign LFSR_N_tmp[8]  = LFSR_tmp[0] ^ LFSR_tmp[15] ^ LFSR_tmp[17] ^ LFSR_tmp[18] ^ LFSR_tmp[19] ^ LFSR_tmp[20] ;
assign LFSR_N_tmp[7]  = LFSR_tmp[17] ^ LFSR_tmp[19] ^ LFSR_tmp[20] ^ LFSR_tmp[21] ;
assign LFSR_N_tmp[6]  = LFSR_tmp[16] ^ LFSR_tmp[18] ^ LFSR_tmp[19] ^ LFSR_tmp[20] ^ LFSR_tmp[22] ;
assign LFSR_N_tmp[5]  = LFSR_tmp[15] ^ LFSR_tmp[17] ^ LFSR_tmp[18] ^ LFSR_tmp[19] ^ LFSR_tmp[21] ^ LFSR_tmp[22] ;
assign LFSR_N_tmp[4]  = LFSR_tmp[17] ;
assign LFSR_N_tmp[3]  = LFSR_tmp[16] ;
assign LFSR_N_tmp[2]  = LFSR_tmp[15] ^ LFSR_tmp[22] ;
assign LFSR_N_tmp[1]  = LFSR_tmp[16] ^ LFSR_tmp[18] ^ LFSR_tmp[20] ^ LFSR_tmp[22] ;
assign LFSR_N_tmp[0]  = LFSR_tmp[15] ^ LFSR_tmp[17] ^ LFSR_tmp[19] ^ LFSR_tmp[21] ^ LFSR_tmp[22] ;

reg [7:0] scr_da_tmp      ;
wire[7:0] scr_da_tmp_n    ;

always @(posedge clk or negedge rst_b)
  begin
   if(!rst_b)
     scr_da_tmp <= #1 8'h0	;
   else if(bypass_scr)
     scr_da_tmp <= #1 dain	;
   else if(EIEOS_ind)
     scr_da_tmp <= #1 dain	;
   else
     scr_da_tmp <= #1 scr_da_tmp_n;
  end

assign scr_da_tmp_n[7] = dain[7] ^ LFSR_tmp[15] ^ LFSR_tmp[17] ^ LFSR_tmp[19] ^ LFSR_tmp[21] ^ LFSR_tmp[22]  ;
assign scr_da_tmp_n[6] = dain[6] ^ LFSR_tmp[16] ^ LFSR_tmp[18] ^ LFSR_tmp[20] ^ LFSR_tmp[22]  ;
assign scr_da_tmp_n[5] = dain[5] ^ LFSR_tmp[17] ^ LFSR_tmp[19] ^ LFSR_tmp[21]  ;
assign scr_da_tmp_n[4] = dain[4] ^ LFSR_tmp[18] ^ LFSR_tmp[20] ^ LFSR_tmp[22]  ;
assign scr_da_tmp_n[3] = dain[3] ^ LFSR_tmp[19] ^ LFSR_tmp[21]  ;
assign scr_da_tmp_n[2] = dain[2] ^ LFSR_tmp[20] ^ LFSR_tmp[22]  ;
assign scr_da_tmp_n[1] = dain[1] ^ LFSR_tmp[21]  ;
assign scr_da_tmp_n[0] = dain[0] ^ LFSR_tmp[22]  ;


endmodule


module LFSR_SHIFT(
                   //input
                   input [22:0]     LFSR_cur          ,                  //current LFST
                   input         datain           ,                  //input data
                   //output
                   output[22:0]     LFSR_next          ,                  //next LFSR
                   output        dataout                              //data out of scramble
                 );



assign LFSR_next[0]   = LFSR_cur[22]                       ;
assign LFSR_next[1]   = LFSR_cur[0]                        ;
assign LFSR_next[2]   = LFSR_cur[1]  ^ LFSR_cur[22]        ;
assign LFSR_next[3]   = LFSR_cur[2]                        ;
assign LFSR_next[4]   = LFSR_cur[3]                        ;
assign LFSR_next[5]   = LFSR_cur[4]  ^ LFSR_cur[22]        ;
assign LFSR_next[6]   = LFSR_cur[5]                        ;
assign LFSR_next[7]   = LFSR_cur[6]                        ;
assign LFSR_next[8]   = LFSR_cur[7]  ^ LFSR_cur[22]        ;
assign LFSR_next[9]   = LFSR_cur[8]                        ;
assign LFSR_next[10]   = LFSR_cur[9]                       ;
assign LFSR_next[11]   = LFSR_cur[10]                      ;
assign LFSR_next[12]   = LFSR_cur[11]                      ;
assign LFSR_next[13]   = LFSR_cur[12]                      ;
assign LFSR_next[14]   = LFSR_cur[13]                      ;
assign LFSR_next[15]   = LFSR_cur[14]                      ;
assign LFSR_next[16]   = LFSR_cur[15]  ^ LFSR_cur[22]      ;
assign LFSR_next[17]   = LFSR_cur[16]                      ;
assign LFSR_next[18]   = LFSR_cur[17]                      ;
assign LFSR_next[19]   = LFSR_cur[18]                      ;
assign LFSR_next[20]   = LFSR_cur[19]                      ;
assign LFSR_next[21]   = LFSR_cur[20]  ^ LFSR_cur[22]      ;
assign LFSR_next[22]   = LFSR_cur[21]                      ;

assign dataout = LFSR_cur[22] ^ datain  ;

endmodule