后端设计中一个很重要的环节就是powerPlan，即电源网络的规划。好的电源网络是要保证逻辑单元能够正常通电，而且IR Drop满足要求，以及规划好了各个电源域的power、ground，保证clp和lvs满足。同时，电源网络又不能过密占用太多绕线资源导致时序受到限制。

下面示例powerplan的脚本实现：

####先打好followpin，保证stdecll能正常供电

setViaGenMode -reset

setViaGenMode -allow_wire_shape_change false

sroute  -connect { corePin } \

        -layerChangeRange { M0 M1 } \

        -allowJogging 0 -allowLayerChange 0 \

        -nets {VDD_cpu VSS}

deleteRouteBlk -name mem_m0_blk

### M1往上，逐层布电源线

setViaGenMode -use_CCE 1

setAddStripeMode -stacked_via_top_layer M1 -stacked_via_bottom_layer M0

setViaGenMode -use_track_offset 1 -optimize_cross_via true

setViaGenMode -viarule_preference {VIA01}

setAddStripeMode -stapling_nets_style side_to_side

addStripe       -layer M1 -area $PGarea \

                -width 0.040 -spacing [expr 0.088] \

                -set_to_set_distance  [expr 0.064*26] \

                -stapling {0.14 1} \

                -snap_wire_center_to_grid Grid \

                -direction vertical \

                -start_offset [expr 0.064*8-0.040/2] \

                -nets {VSS VSS}

addStripe       -layer M1 -area $PGarea \

                -width 0.040 -spacing [expr 0.088] \

                -set_to_set_distance  [expr 0.064*26] \

                -stapling {0.14 1} \

                -snap_wire_center_to_grid Grid \

                -direction vertical \

                -start_offset [expr 0.064*8-0.040/2] \

                -nets {VDD_CPU VDD_CPU}

deselectAll

editSelect -type Special -layer 2

editStretch y -0.02 high -no_conn 1

editStretch y 0.02 low -no_conn 1

deselectAll

### M2

## please adjust 0.956 0.076*13+core2left

setViaGenMode -use_CCE 1

setAddStripeMode -stacked_via_top_layer M2 -stacked_via_bottom_layer M1

setViaGenMode -use_track_offset 1 -optimize_cross_via true

setViaGenMode -viarule_preference {VIA12_1cut_BW40_UW20}

#setViaGenMode -viarule_preference {VIA12_1cut_BW37_UW20}

setAddStripeMode -stapling_nets_style side_to_side

set offset [expr 0.064*9]

set layer_pitch [expr 0.064*26]

addStripe       -layer M2 -area $PGarea \

                -width 0.020 -spacing [expr 0.28] \

                -set_to_set_distance  [expr 0.6] \

                -stapling {0.403 0.576 0.832:2} \

                -snap_wire_center_to_grid Grid \

                -direction horizontal\

                -start_offset [expr 0.29] \

                -nets {VSS VDD_CPU}

### M3

set layer M3

setViaGenMode -reset

setViaGenMode -use_track_offset 1 -optimize_cross_via true

setViaGenMode -viarule_preference {VIA23_1cut_BW20_UW24}

setAddStripeMode -stacked_via_top_layer M3 -stacked_via_bottom_layer M2

addStripe       -layer $layer -area $PGarea \

                -width 0.024 -spacing [expr 0.044*3 -0.022] \

                -set_to_set_distance  [expr 0.064*26] \

                -direction vertical \

                -snap_wire_center_to_grid Grid \

                -start_offset [expr 0.044*9+0.044/2] \

                -nets {VDD_CPU VDD_CPU}

addStripe       -layer $layer -area $PGarea \

                -width 0.024 -spacing [expr 0.044*3] \

                -set_to_set_distance  [expr 0.064*26] \

                -direction vertical \

                -snap_wire_center_to_grid Grid \

                -start_offset [expr 0.044*11+0.044/2] \

                -nets {VSS VSS}

colorizeGeometry

##至此double pattern层的电源线布线完成，再往上的命令使用类似，就不赘述。