1)Static Timing Analysis (also referred as STA) is one of the many techniques available to verify the timing of a digital design.

2) The STA is static since the analysis of the design is carried out statically and does not depend upon the data values being applied at the input pins.

3)Given a design along with a set of input clock definitions and the definition of the external environment of the design, the purpose of static timing analysis is to validate if the design can operate at the rated speed.

4) The more important aspect of static timing analysis is that the entire design is analyzed once and the required timing checks are performed for all pos- sible paths and scenarios of the design. Thus, STA is a complete and ex- haustive method for verifying the timing of a design.

2. Why Static Timing Analysis?

2) Static timing analysis on the other hand provides a faster and simpler way of checking and analyzing all the timing paths in a design for any timing violations.

3.What's a setup check?

A setup check ensures that the data can arrive at a flip-flop within the given clock period. 

4.What's a hold check?

A hold check ensures that the data is held for at least a minimum time so that there is no unexpected pass-through of data through a flip-flop: that is, it ensures that a flip-flop captures the intended data correctly.

5. What is the impact of noise and crosstalk?

1)For deep submi-cron or nanometer process technologies1, the coupling in the interconnect induces noise and crosstalk - either of which can limit the operating speed of a design.

2)The design functionality and its performance can be limited by noise. The noise occurs due to crosstalk with other signals or due to noise on primary inputs or the power supply

  4)Verification based upon logic simulation cannot handle the effects of cross- talk, noise and on-chip variations.

7. During which phase of the over- all design process are these analyses applicable.

   (1) Once a design at RTL level has been synthesized to gate level, the STA is used to verify the timing of the design.

    (2)STA can also be run prior to performing logic optimization - the goal is to identify the worst or critical timing paths.

    (3)STA can be rerun after logic optimization to see whether there are failing paths still remaining that need to be optimized, or to identify the critical paths.

    (4) Once the physical design starts and after clock trees are built, STA can be performed to check the timing again

    (5) during physical design, STA can be performed at each and every step to identify the worst paths.

8. How to deal with RC in difference phase?

        STA can be performed assuming interconnects as ideal, or using a wireload model, assuming clock trees as ideal or real, assuming global routes, or using real routes for parasitics.

    (1) WLM phase: At the logical design phase, ideal interconnect may be assumed since there is no physical information related to the placement. Another technique used at this stage is to estimate the length of the interconnect using a wireload model. The wireload model provides estimated RC based on the fanouts of a cell.

    (2) Global route phase :Before the routing of traces are finalized, the implementation tools use an estimate of the routing distance to obtain RC parasitics for the route. Since the routing is not finalized, this phase is called the global route phase. During this phase, one can not include the effect of coupling.

    (3) Final route phase: After the detailed routing is complete, actual RC values obtained from extraction are used and the effect of coupling can be analyzed. However, a physical design tool may still use  approximations to help improve run times in computing RC values.  

    (4) SPF/SPEF: An extraction tool is used to extract the detailed parasitics (RC values) from a routed design. Such an extractor may have an option to obtain parasitics with small runtime and less accurate RC values during iterative optimization and another option for final verification during which very accurate RC values are extracted with a larger runtime.

9. The static timing analysis can be performed on a gate-level netlist depending on:

     i. How interconnect is modeled - ideal interconnect, wireload model, global routes with approximate RCs, or real routes with accurate RCs.
     ii. How clocks are modeled - whether clocks are ideal (zero delay) or propagated (real delays).
    iii. Whether the coupling between signals is included - whether any crosstalk noise is analyzed.

10. What's kind of flow the STA can be used to ?

    (1) CMOS Digital Designs(ASIC flow)

    (2) FPGA Designs

    (3) Asynchronous Designs

11. Limitations of Static Timing Analysis

    (1) The state-of-the-art still does not allow STA to replace simulation completely;

    (2) Can't check Reset sequence to check if f all flip-flops are reset into their required logical values after an asynchronous or synchronous reset.

    (3) Can't check X-handling: X-handling: The STA techniques only deal with the logical domain of logic-0 and logic-1 (or high and low), rise and fall. An unknown value X in the design causes indeterminate values to propagate through the design, which cannot be checked with STA.

    (4) PLL settings: PLL configurations may not be loaded or set properly.

    (5) Asynchronous clock domain crossings:

    (6) IO interface timing:

    (7) Interfaces between analog and digital blocks:

    (8) False paths:

    (9) FIFO pointers out of synchronization

    (10) Clock synchronization logic:STA cannot detect the problem of
clock generation logic not matching the clock definition

    (11) Functional behavior. across clock cycles:The static timing analysis
cannot model or simulate functional behavior. that changes across clock cycles.

12. What's kind of check the STA focus on?

     The concepts of computing cell delays, timing a combinational block, clock relationships, multiple clock domains and gated clocks form. an important basis for static timing analysis.