Link: https://www.eetimes.com/document.asp?doc_id=1278980
A latch is a level-sensitive storage cell that is transparent to signals passing from the D input to output Q when enabled, and that holds the values of D on Q as of the time enable goes False. The enabled state is also called transparent state. Depending on the polarity of the enable input, we call latches positive-level or negative-level.

(1) Wath's the advantage and disadvantage of latch and flipflop?
      Latch :
      1) Borrow time from the open edge to close edge;
      2) Latch-based designs have small die size, it's size is half of flipflop;
      3) Can used to build more fast circuit than flipflop, more successful in high-speed designs where clock frequency is in GHz
       4) Also when process variation is considered, latch-based design is dramatically more variation-tolerant

(2) How to do Setup/Hold violation check(same_level latch)?
     1) Same_level latch

     1st latch clock sequence {1o1,1c1,1o2,1c2,1o3,1c3}, 2nd latch clock sequence {2o1,2c1,2o2,2c2,2o3,2c3}, and have delay between those two latch clock.
     setup(max): 1o1 edge data to 2c1 edge clock(trace back to 2o1 edge)
     hold(min): 1o2 data to 2c1 clock

    2) Different_level latch
        1st negative_level latch({1o1,1c1,1o2,1c2,1o3,1c3});
         2nd positive_level latch{{2o1,2c1,2o2,2c2,2o3,2c3}};
          setup(max): 1o1 edge data to 2c1 edge clock(trace back to 2o1 edge)
           hold(min): 1o2 data to 2c1 clock

(3) What's will be check if when we "set_multicycle_path -setup -end 0"?
      setup(max): 1o2 data to 2o1 clock (timing borrowed from endpoint)
      hold(min): 1o3 data to 2c1clock (Time meet more than one clock period)
      Note: lath shouldn't set "set_multicycle_path -setup -end 0"