日志
以 inverter 检验IC设计流程
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Inverter电路图
直流仿真
瞬时仿真
Inverter版图
DRC 报告：
Validating hierarchy instantiation for:
library: Inverter_tutorial
cell: inverter
view: layout
Rules path is divaDRC.rul.
Inclusion limit is set to 1000.
。。。
Optimizing rules...
removing unused task: nwellResEdge = geomGetEdge(nwellRes coincident nwell)
removing unused task: polyResEdge = geomGetEdge(polyRes coincident poly)
removing unused task: elecEdge = geomGetEdge(elec)
removing unused task: padEdge = geomGetEdge(pad)
removing unused task: ccEdge = geomGetEdge(cc)
removing unused task: gselectEdge = geomGetEdge(gselect)
removing unused task: gwellEdge = geomGetEdge(gwell)
removing unused task: nwellRes = geomButting(geomAnd(res_id nwell) nBulk (keep == 2))
removing unused task: polyRes = geomButting(geomAnd(res_id poly) fieldPoly (keep == 2))
removing unused task: NwPdiode = geomAnd(dio_id geomOutside(nwell pNotOhmic))
removing unused task: PNdiode = geomAnd(dio_id geomOutside(pNotOhmic poly))
removing unused task: NPdiode = geomAnd(dio_id geomOutside(nNotOhmic poly))
removing unused task: m3m2Cap = geomAnd(geomAnd(metal2 metal3) cap_id)
removing unused task: m2m1Cap = geomAnd(geomAnd(metal1 metal2) cap_id)
removing unused task: m1sCap = geomAnd(geomAndNot(metal1 poly) cap_id)
removing unused task: m1pCap = geomAnd(geomAnd(poly metal1) cap_id)
removing unused task: pChannelCap = geomButting(pChannel pDiff (keep == 1))
removing unused task: nChannelCap = geomButting(nChannel nDiff (keep == 1))
removing unused task: pChannelTran = geomButting(pChannel pDiff (keep == 2))
removing unused task: nChannelTran = geomButting(nChannel nDiff (keep == 2))
removing unused task: Space = geomNot(geomOr(active poly elec))
removing unused task: pElecChannelCap = geomButting(pElecChannel pDiff (keep == 1))
removing unused task: nElecChannelCap = geomButting(nElecChannel nDiff (keep == 1))
removing unused task: pElecChannelTran = geomButting(pElecChannel pDiff (keep == 2))
removing unused task: nElecChannelTran = geomButting(nElecChannel nDiff (keep == 2))
removing unused task: pElecChannel = geomOutside(geomAnd(pNotOhmic elec) poly)
removing unused task: nElecChannel = geomOutside(geomAnd(nNotOhmic elec) poly)
removing unused task: pChannel = geomOutside(geomAnd(pNotOhmic poly) elec)
removing unused task: nChannel = geomOutside(geomAnd(nNotOhmic poly) elec)
removing unused task: dio_id = geomOr("dio_id")
removing unused task: cap_id = geomOr("cap_id")
removing unused task: nolpe = geomOr("nolpe")
removing unused task: bkgnd = geomBkgnd()
Running layout DRC analysis
Flat mode
Full checking.
DRC started.......Mon Jan 2 18:52:44 2017
completed ....Mon Jan 2 18:52:44 2017
CPU TIME = 00:00:00 TOTAL TIME = 00:00:00
********* Summary of rule violations for cell "inverter layout" *********
Total errors found: 0
LVS报告：
Like matching is enabled.
Net swapping is enabled.
Using terminal names as correspondence points.
Net-list summary for /home/Projects/CMOSedu/LVS/layout/netlist
count
4 nets
4 terminals
1 pmos
1 nmos
Net-list summary for /home/Projects/CMOSedu/LVS/schematic/netlist
count
4 nets
4 terminals
1 pmos
1 nmos
Terminal correspondence points
N2 N2 A
N3 N0 Ai
N1 N1 gnd
N0 N3 vdd
Devices in the netlist but not in the rules:
pmos nmos
The net-lists match.
layout schematic
instances
un-matched 0 0
rewired 0 0
size errors 0 0
pruned 0 0
active 2 2
total 2 2
nets
un-matched 0 0
merged 0 0
pruned 0 0
active 4 4
total 4 4
terminals
un-matched 0 0
matched but
different type 0 0
total 4 4
Probe files from /home/Projects/CMOSedu/LVS/schematic
devbad.out:
netbad.out:
mergenet.out:
termbad.out:
prunenet.out:
prunedev.out:
audit.out:
Probe files from /home/Projects/CMOSedu/LVS/layout
devbad.out:
netbad.out:
mergenet.out:
termbad.out:
prunenet.out:
prunedev.out:
audit.out:
反相器做整形电路
整形效果：
/1 
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