日志

timing loop

已有 3968 次阅读| 2017-5-4 16:14 |个人分类:FPGA|系统分类:硬件设计

vivado warning, wire信号陷入循环赋值。

解决：检查赋值或改为reg类型。

同样的问题会引起modelsim出错：

this error usually indicates that ModelSim is stuck in an infinite loop. In Vhdl, this can happen when a signal is placed in the sensitivity list and this signal is changed in the process. The signal changes, triggering the process, which changes the signal, which again triggers the process and the cycle continues.

The following is a simple example of a process that causes an infinite loop:

PROCESS (count)

BEGIN

count <= not count;

END PROCESS;