By Joel Hruska on June 23, 2014 at 10:01 am

If you pay any degree of attention to the semiconductor market, the back-and-forth between what is and isn’t possible is liable to give you whiplash. One day we’re talking about silicon hitting a wall at 14nm, and other days we’re talking about pushing towards 5nm and beyond. Reports of profound difficulties and industry delays are interspersed with breathless discussions of new technology, capabilities, and options for continuing to improve semiconductor designs. A new article straddles these two views with a discussion of future CMOS technologies, while simultaneously acknowledging that it’s not clear how many companies will push below the 10nm node.

The complexities of “Will it work?”

Ask an economist and an engineer if sub-10nm manufacturing can work and you’re likely to get two completely different answers. These two perspectives often tangle in the comment threads in these types of stories, with some people insisting that we’ll find a way to build better, faster processors, while the more economically-minded focus on the rising cost of transistors and the severe cost pressure this creates.

According to Semiengineering, the industry is evaluating a wide range of technologies for the sub-10nm node including gate-all-around FETs (also called nanowires), quantum well FETs, and silicon-on-insulator FinFETs. Quantum well FETs remain mired in uncertainty while SOI FinFETs continue SOI’s longstanding approach of being the best solution no one ever uses. (Alright, that’s not quite fair. We hear it’s huge in Korea.) That leaves gate-all-around FETs as the most likely approach at 7nm, with germanium as a channel option. This assumes certain difficulties of adapting germanium for the n-channel can be overcome — currently germanium is an excellent p-channel material but more difficult to work with for an n-channel.

III-V semiconductors, which were originally expected to debut at 10nm, are now being pushed back to 7nm or 5nm due to ongoing manufacturing difficulties. EUV remains a consistent challenge, and though manufacturers swear they’ll solve the power problem, the difficulties are staggering. Gate-all-around is an attractive method for improving transistor performance, but manufacturers are still struggling to hit reliability and dimension challenges. Materials like graphene or carbon nanotubes meanwhile, won’t debut for a decade or more in complex CMOS logic devices.

Slow caches can recognize substantial gains over 28nm, but fast cache will scarcely improve over the current generation

This brings us back to the economics question, which is ultimately where the fight will be decided. The question isn’t whether we can continue building to lower process nodes (with the understanding that “node” is merely a label for a group of technologies that deliver an improvement rather than a measure of half-pitch or gate length). The question is whether it makes economic sense to do so. SRAM cells are only getting about 10% smaller per node shrink — they don’t scale very well compared to traditional logic. Other areas (I/O, contact pads) don’t really scale at all.

This creates long-term problems for manufacturers looking to scale designs to smaller nodes, dilutes the value of doing so, and — with costs per node now rising instead of falling — puts increased pressure on design teams. In response, companies like Qualcomm are turning towards different layout methods; the company is now pursuing a monolithic 3D die structure rather than a conventional planar implementation.

This is one area where silicon photonics could play a major role in the future by reducing the power consumption and delay of sending signals over wires, but for now, Qualcomm is planning to work with normal vias and technology. According to the company, a monolithic 3D IC could provide a 30% power savings, 40% performance boost, and cut cost by 5-10% — without changing over to a new node.

The decreasing importance of “nodes”

We’re already seeing the end of conventional planar CMOS scaling. TSMC shipped 28nm silicon in 2012, it’ll ship 20nm by the end of 2014 or early 2015 — but the 20nm it ships will be only modestly better than existing 28nm. By the time we see 16nm — which truly improves on 28nm — 2016 will be right around the corner. Sure, companies will keep a two-year cadence for marketing purposes, but the equivalent improvement cycle has pushed out to three years from two. Even Intel has been bitten by the bug — it took the company 27 months to move from 32nm to 22nm and 31-32 months (depending on the launch date) to move from 22nm to 14nm for Broadwell — and that assumes it keeps its current launch target.

Marketing departments at chip companies are going to continue to talk about new nodes because customers are conditioned to expect them. It’s the semiconductor equivalent of Pavlov’s bell, and I don’t expect it will change in the near future. What’s increasingly obvious, however, is that companies are going to start experimenting with new design structures and capabilities in an attempt to defray lithography cost. Qualcomm is talking about monolithic 3D dies, through-silicon vias (TSVs) and other elements of design that cut die space or reduce transistor counts without requiring a node shrink will be increasingly essential.

I’m certain the semiconductor industry will arrive at what it refers to as 7nm and 5nm because that’s what the semiconductor industry does. Whether or not those improvements actually correspond to major lithography changes will be a different story altogether. I suspect that rather than focusing solely on the implementation of new lithgography technology, future nodes will be driven by design improvements — TSMC might declare 7nm to be the node at which it can offer III-V materials and a 3D stacked die with TSVs, rather than just basing the node declaration around physical characteristics.