VCS对verilog模型进行仿真包括两个步骤:
1. 编译verilog文件成为一个可执行的二进制文件命令为:vcs source_files2. 运行该可执行文件:./simv
类似于NC, 也有单命令行的方式:vcs source_files -R-R 命令表示, 编译后立即执行。
vcs常用的命令选项如下:-cm line|cond|fsm|tgl|obc|path 设定coverage的方式+define+macro=value+ 预编译宏定义-f filename RTL文件列表+incdir+directory+ 添加include 文件夹-I 进入交互界面-l logfile文件名-P pli.tab 定义PLI的列表(Tab)文件+v2k 使用推荐的标准-y 定义verilog的库-notice 显示详尽的诊断信息-o 指定输出的可执行文件的名字,缺省是simv+ nospecify 不对SPECIFY 模块进行时序检查和路径延时计算+ notimingcheck 不进行时序检查;但是还是把path延时加入仿真中 Summary of vcs compile options:-ASFLAGS "opts" pass 'opts' to the assembler-B generate long call instructions in native assembly code (HP only)-CC "opts" pass 'opts' to C compiler-CFLAGS "opts" pass 'opts' to C compiler-LDFLAGS "opts" pass 'opts' to C compiler on load line only-I enable interactive/postprocessing debugging capabilities-ID get host identification information-M enable incremental compilation (see manual)-Mupdate enable incremental compilation and keep the Makefile up-to-date-Marchive[=N] create intermediate libs to reduce link line length; N objs per lib-P plitab compiles user-defined pli definition table 'plitab'-PP enable optimizer postprocessing capabilities for vcd+-R after compilation, run simulation executable-RI after compilation, run simulation under xvcs (Implies -I)-RIG run simulation under xvcs without compiling (executable has to exist)-RPP run xvcs in postprocessing mode (requires file created by vcdpluson)-V[t] verbose mode; with 't', include time information-as foo use foo as the assembler-cc foo use foo as the C compiler-cpp foo use foo as the C++ compiler-e specify the name of your main() routine. (see manual section 7-11 for more details).-f file reads 'file' for other options-gen_c generate C code (for HP and Sun, default is -gen_obj)-gen_asm generate native assembly code (HP and Sun only)-gen_obj generate native object code (HP and Sun only)-ld foo use foo as the linker. (refer vcs manual for compatibility with -cpp option)-line enable single-stepping/breakpoints for source level debugging-lmc-swift include lmc swift interface-lmc-hm include lmc hardware modeler interface-vera add VERA 4.5+ libraries-vera_dbind add VERA 4.5+ libraries for dynamic binding-location display full pathname to vcs installation for this platform.-vhdlobj generate a vhdl obj for simulating in a vhdl design-mixedhdl include MixedHDL-1.0 interface-mhdl include MixedHDL-2.0 interface and library-q quiet mode-platform. display name of vcs installation subdirectory for this platform.-syslib 'libs' specify system libraries (placed last on the link line) eg -lm-o exec name the executable simulation model 'exec' (default is 'simv')-u treat all non text string characters as uppercase-v file search for unresolved module references in 'file'-y libdir search for unresolved module references in directory 'libdir'+acc enable pli applications to use acc routines (see manual)+ad include anlog simulation interface and library+adfmi="files" ADFMI support for vcs-ace+cliedit enable command line edit/recall (see doc/readline.ps)+cli enable command line interactive debugging (see manual)+cmod Enabling cmodule feature+cmodext+cmodext Changing cmodule extension to cmodext+cmodincdir+cmoddir Cmodule Include directory+cmoddefine+macro define cmodule source 'macro' in the form. of XX=YY+define+macro define hdl source 'macro' to have value "macro"+plusarg_save hardwire the plusargs, which follow this flag, into simv+plusarg_ignore turn off +plusarg_save+prof tells vcs to profile the the design and generate vcs.prof file+race tells vcs to generate a report of all race conditions and write this report in the race.out file+rad+1 enable level 1 radiant optimizations (See Release Notes)+rad+2 enable level 2 radiant optimizations (See Release Notes)+libext+lext use extension 'lext' when searching library directorys+librescan search from beginning of library list for all undefined mods+incdir+idir for `include files, search directory 'idir'+nospecify suppress path delays and timing checks+notimingchecks suppress timing checks+optconfigfile+foo use 'foo' as the optimization config file (See Release Notes)+vcsd enable the VCS Direct sim kernel interface-cmhelp enable CoverMeter help-cm enable VCS to first run cmSource to instrument the Verilog source files on the command line-cm_all enable VCS to link CoverMeter into the VCS executable in a way that enables all coverages-cm_lineonly enable VCS to link CoverMeter into the VCS executable in a way that only enables line coverage
- +v2k
- Enables language features in the IEEE 1364-2001 standard.
- success报告成功匹配
- Enables reporting of successful matches, and successes on
- cover statements, in addition to failures. The default is to report
- only failures.
-
-
- filter过滤掉空成功。
- Blocks reporting of trivial implication successes. These happen
- when an implication construct registers a success only because
- the precondition (antecedent) portion is false (and so the
- consequent portion is not checked). With this option, reporting
- only shows successes in which the whole expression matches.
-
-
- -assert filter+success经常两者结合起来用。注意用时在filter+success前加上-assert
-
- maxsuccess=N
- Limits the total number of reported successes to N. You must
- supply N, otherwise no limit is set. VCS continues to monitor
- assertions even after the limit is reached.
-
- -assert maxsuccess=3
-
- -l filename logfile文件名
- Specifies a file where VCS records compilation messages. If you
- also enter the -R or -RI option, VCS records messages from both
- compilation and simulation in the same file.
-
-
- -assert enable_diag
- Enables further control of results reporting with runtime options
-
- -sverilog
- Enables the use of SystemVerilog code.
-
- -cm assert
- Compiles for SystemVerilog assertions coverage. -cm is not a
- new compile-time option but the assert argument is new. This
- option and argument must also be entered at runtime.
-
-
-
- vcs *.v *.sva -sverilog \
- +define+enable_blk_assertions \
- +define+tb_sva \
- +define+slv_fc \
- +define+slv_doc \
- -PP -assert enable_diag -cm assert \
- -l compile.log
-
-
- simv -l run.log -assert filter+success -assert maxsuccess=3
-
- VCS对verilog模型进行仿真包括两个步骤:
- 1. 编译verilog文件成为一个可执行的二进制文件命令为:
- {1}gt; vcs source_files
-
- 2. 运行该可执行文件
-