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VCS仿真命令

已有 7712 次阅读| 2016-11-1 16:33 |个人分类:仿真工具|系统分类:芯片设计

VCS对verilog模型进行仿真包括两个步骤:

1. 编译verilog文件成为一个可执行的二进制文件命令为:vcs source_files

2. 运行该可执行文件:./simv


类似于NC, 也有单命令行的方式:vcs source_files -R

-R 命令表示, 编译后立即执行。


vcs常用的命令选项如下:
-cm line|cond|fsm|tgl|obc|path  设定coverage的方式
+define+macro=value+      预编译宏定义
-f filename             RTL文件列表
+incdir+directory+         添加include 文件夹
-I                 进入交互界面
-l                 logfile文件名
-P pli.tab              定义PLI的列表(Tab)文件
+v2k                使用推荐的标准
-y                  定义verilog的库
-notice               显示详尽的诊断信息
-o                  指定输出的可执行文件的名字,缺省是simv
+ nospecify            不对SPECIFY 模块进行时序检查和路径延时计算
+ notimingcheck           不进行时序检查;但是还是把path延时加入仿真中
 
Summary of vcs compile options:
-ASFLAGS     "opts" pass 'opts' to the assembler
-B         generate long call instructions in native assembly code (HP only)
-CC        "opts" pass 'opts' to C compiler
-CFLAGS      "opts" pass 'opts' to C compiler
-LDFLAGS     "opts" pass 'opts' to C compiler on load line only
-I         enable interactive/postprocessing debugging capabilities
-ID         get host identification information
-M          enable incremental compilation (see manual)
-Mupdate      enable incremental compilation and keep the Makefile up-to-date
-Marchive[=N]   create intermediate libs to reduce link line length; N objs per lib
-P plitab      compiles user-defined pli definition table 'plitab'
-PP          enable optimizer postprocessing capabilities for vcd+
-R          after compilation, run simulation executable
-RI         after compilation, run simulation under xvcs (Implies -I)
-RIG         run simulation under xvcs without compiling (executable has to exist)
-RPP         run xvcs in postprocessing mode (requires file created by vcdpluson)
-V[t]          verbose mode; with 't', include time information
-as          foo use foo as the assembler
-cc          foo use foo as the C compiler
-cpp         foo use foo as the C++ compiler
-e    specify the name of your main() routine. (see manual section 7-11 for more details).
-f file          reads 'file' for other options
-gen_c          generate C code (for HP and Sun, default is -gen_obj)
-gen_asm       generate native assembly code (HP and Sun only)
-gen_obj        generate native object code (HP and Sun only)
-ld           foo use foo as the linker. (refer vcs manual for compatibility with -cpp option)
-line           enable single-stepping/breakpoints for source level debugging
-lmc-swift        include lmc swift interface
-lmc-hm        include lmc hardware modeler interface
-vera           add VERA 4.5+ libraries
-vera_dbind      add VERA 4.5+ libraries for dynamic binding
-location        display full pathname to vcs installation for this platform.
-vhdlobj    generate a vhdl obj for simulating in a vhdl design
-mixedhdl        include MixedHDL-1.0 interface
-mhdl          include MixedHDL-2.0 interface and library
-q            quiet mode
-platform.        display name of vcs installation subdirectory for this platform.
-syslib         'libs' specify system libraries (placed last on the link line) eg -lm
-o           exec name the executable simulation model 'exec' (default is 'simv')
-u            treat all non text string characters as uppercase
-v file          search for unresolved module references in 'file'
-y libdir          search for unresolved module references in directory 'libdir'
+acc           enable pli applications to use acc routines (see manual)
+ad             include anlog simulation interface and library
+adfmi="files"      ADFMI support for vcs-ace
+cliedit           enable command line edit/recall (see doc/readline.ps)
+cli             enable command line interactive debugging (see manual)
+cmod           Enabling cmodule feature
+cmodext+cmodext    Changing cmodule extension to cmodext
+cmodincdir+cmoddir    Cmodule Include directory
+cmoddefine+macro    define cmodule source 'macro' in the form. of XX=YY
+define+macro       define hdl source 'macro' to have value "macro"
+plusarg_save       hardwire the plusargs, which follow this flag, into simv
+plusarg_ignore      turn off +plusarg_save
+prof           tells vcs to profile the the design and generate vcs.prof file
+race          tells vcs to generate a report of all race conditions and write this report in the race.out file
+rad+1           enable level 1 radiant optimizations (See Release Notes)
+rad+2           enable level 2 radiant optimizations (See Release Notes)
+libext+lext         use extension 'lext' when searching library directorys
+librescan         search from beginning of library list for all undefined mods
+incdir+idir         for `include files, search directory 'idir'
+nospecify         suppress path delays and timing checks
+notimingchecks     suppress timing checks
+optconfigfile+foo   use 'foo' as the optimization config file (See Release Notes)
+vcsd          enable the VCS Direct sim kernel interface
-cmhelp         enable CoverMeter help
-cm          enable VCS to first run cmSource to instrument the Verilog source files on the command line
-cm_all      enable VCS to link CoverMeter into the VCS executable in a way that enables all coverages

-cm_lineonly  enable VCS to link CoverMeter into the VCS executable in a way that only enables line coverage 




  1. +v2k  
  2. Enables language features in the IEEE 1364-2001 standard.   

 
  1. success报告成功匹配  
  2. Enables reporting of successful matches, and successes on   
  3. cover statements, in addition to failures. The default is to report   
  4. only failures.  
  5.   
  6.   
  7. filter过滤掉空成功。  
  8. Blocks reporting of trivial implication successes. These happen   
  9. when an implication construct registers a success only because   
  10. the precondition (antecedent) portion is false (and so the   
  11. consequent portion is not checked). With this option, reporting   
  12. only shows successes in which the whole expression matches.  
  13.   
  14.   
  15. -assert filter+success经常两者结合起来用。注意用时在filter+success前加上-assert  
  16.   
  17. maxsuccess=N  
  18. Limits the total number of reported successes to N. You must   
  19. supply N, otherwise no limit is set. VCS continues to monitor   
  20. assertions even after the limit is reached.  
  21.   
  22. -assert maxsuccess=3  
  23.   
  24. -l filename logfile文件名  
  25. Specifies a file where VCS records compilation messages. If you   
  26. also enter the -R or -RI option, VCS records messages from both   
  27. compilation and simulation in the same file.  
  28.   
  29.   
  30. -assert enable_diag  
  31. Enables further control of results reporting with runtime options  
  32.   
  33. -sverilog  
  34. Enables the use of SystemVerilog code.  
  35.   
  36. -cm assert  
  37. Compiles for SystemVerilog assertions coverage. -cm is not a   
  38. new compile-time option but the assert argument is new. This   
  39. option and argument must also be entered at runtime.  
  40.   
  41.   
  42.   
  43. vcs *.v *.sva -sverilog \  
  44. +define+enable_blk_assertions \  
  45. +define+tb_sva \  
  46. +define+slv_fc \  
  47. +define+slv_doc \  
  48. -PP -assert enable_diag -cm assert \  
  49. -l compile.log  
  50.   
  51.   
  52. simv -l run.log -assert filter+success -assert maxsuccess=3  
  53.   
  54. VCS对verilog模型进行仿真包括两个步骤:  
  55.   1. 编译verilog文件成为一个可执行的二进制文件命令为:  
  56.     {1}gt; vcs source_files  
  57.   
  58.   2. 运行该可执行文件  

  59. 点赞

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