Binding SVA module to design can be done using system verilog bind statement. This is semantically equivalent to instantiation of SVA module. The bind directive can be specified in a module, interface or a compilation unit scope.
There are many ways binding can be done. Following section discusses these.
Normal Bind
Binding fifo to fifo_sva assertion module can be done as follows
Bind using Implicit port connections
By using this method, port names need not be specified and all ports will be accessible to assertion module.
Bind to a lower level module
Hierarchy needs to be specified along with the bind statement.
Bind using different parameters/generic
Passing parameter values in bind can be done in the following way.
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