日志

04 uvm_sequence

已有 1255 次阅读| 2019-7-11 11:40 |个人分类:UVM|系统分类:芯片设计

1. Overview

用来产生激励，由sequencer发送sequence_item给driver

1.1 和uvm_sequence有关的method

1.2 uvm_sequence基本的执行流程

1.2.1 uvm_driver:

Driver header: class driver extends uvm_driver #(transaction)

Driver request: 通过seq_item_port.get_next_item(req)实现

Driver process: 根据具体的protocol, interface实现

Driver set sequence item done flag: 使用seq_item_port.item_done()实现

1.2.2 uvm_sequence:

sequence header: class tr_sequence extends uvm_sequence #(transaction);

sequence body: start() 会调用body()

if (starting_phase != null) starting_phase.raise_objection(this, "starting");

`uvm_do(req); // uvm_do_with, uvm_do_on

if (starting_phase != null) starting_phase.drop_objection(this, "done");

1.2.3 sequence callback:

start(sequencer, parent_sequence, priority, call_pre_post) flow: pre_start() -> pre_body() -> body() -> post_body() -> post_start()

pre_body(): if call_pre_post == 1 for sub-sequences

post_body(): if call_pre_post == 1 for sub-sequences

body(): simulate code

2. base sequence: 一般就是用来加raise/drop_objections

2.1 base_seqeunce:

class base_sequence extends uvm_sequence #(transaction);

virtual task pre_start();

if (get_parent_sequence() == null && starting_phase != null)

starting_phase.raise_objection(get_sequencer());

endtask

virtual task post_start

if (get_parent_sequence() == null && starting_phase != null)

starting_phase.dropt_objection(get_sequencer());

endtask

endclass: base_sequence

2.2 真正有用的sequence需要从base_sequence extend，加入body task

3. simulate代码在body中实现

3.1 自动

`uvm_do，`uvm_do_with, `uvm_do_on

3.2 手动

·uvm_create_on(req, m_sequencer);

start_item(req); // 等待parent_sequencer从driver获得request

req.addr = 3; ... // 创建用户自己的数据

finish_item(req); //使用parent sequencer把item传递给driver，然后等待done

4. start_item, finish_item的顺序，下面不是实际代码

task start_item(req); task fnish_item(req);

seqr.wait_for_grant(); seqr.send_request(req);

seqr.begin_tr(req); seqr.wait_for_item_done();

endtask seqr.end_tr(req);

endtask

5. 如何实现randc

`uvm_do不支持randc的变量

解决方法

virtual task body();

`uvm_create(req);

repeat(10) begin

transaction req_copy;

start_item(req);

req.randomize();

`uvm_create(req_copy);

req_copy.copy(req);

finish_item(req_copy);

end

endtask

6. scenario

一连串的sequence组成

7. 从test中设置变量的值

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