1. 3-step flow -- for mixed vhdl and verilog language
vhdlan [comp_option] <-f vhdl_file_list>
vlogan [comp_otpion] uvm // need to compile uvm independently
vlogan [comp_option[ <-f vlog_file_list>
vcs //emulate
simv // run simulation
2. 2-step flow -- for single language
vcs [comp_option] <-f rtl_file_list>
simv