| ||
interface param_if#(int width = 8);
logic clk;
logic[width-1:0] data;
clocking active_cb @(posedge clk);
default input #1 output #1;
output data;
endclocking
modport active_mp (clocking active_cb);
endinterface
typedef virtual param_if param_vif
module test_top;
param_if#(8) if8();
param_if#(16) if16();
param_if#(32) if32();
initial begin
uvm_config_db#(virtual param_if#(8))::set(uvm_root::get(), "uvm_test_top.param_agent8", "vif", if8);
uvm_config_db#(virtual param_if#(16))::set(uvm_root::get(), "uvm_test_top.param_agent16", "vif", if16);
uvm_config_db#(virtual param_if#(32))::set(uvm_root::get(), "uvm_test_top.param_agent32", "vif", if32);
run_test("cust_test");
end
endmodule