The big news of the morning was that Intel has discovered a “design error” in a 65nm support chip for their new Sandy Bridge based systems, affecting the SATA disk-drive I/O controller.

“The chipset is utilized in PCs with Intel’s latest Second Generation Intel Core processors, code-named Sandy Bridge. Intel has stopped shipment of the affected support chip from its factories.”

Apparently the problem is not “functional“, and is due to “degradation” of performance that was discovered post-silicon during the company’s “ongoing QA“.  In their update conference call, Intel said the root cause was due to “a design oversight“, and could be fixed in one of the “later layers of metal“.

This news broke just as I was rushing to meet a deadline for my upcoming article on IC simulation and verification. As they say, timing is everything! If ever there was a great lead-in for an article on the challenges of design verification, this is it. It almost writes itself (well almost… in my dreams)!

The impact is staggering in dollar terms, even if you are a $40B+ company.

“Total cost to repair and replace affected materials and systems in the market is estimated to be $700 million.“

And I used to lose sleep before a tapeout that had tens of thousands of dollars at risk!

Credit goes to Intel for the prompt disclosure and explanation. We can infer a few things from the information provided.

1.  Degradation over time can be associated with  NBTI (negative-bias temperature instability) or HCI (hot-carrier injection). Intel has published reports on these phenomena in their Journal.
2. It is very difficult to model and simulate these aging effects, and a 65nm chip may have been thought to be immune.
3. Improper biasing, or mismatching of a higher voltage domain to a lower voltage device can contribute to such problems.
4. Since the device was still functional, but degraded over time (as much as 3 years according to Intel), my guess is that the metal fix is to correct a supply rail or bulk connection error.

There are many lessons here… big ones!

• First, functional verification is not sufficient to ensure a successful tapeout, even if you can get to 100% coverage.
• Analog verification is just as important, maybe more important than digital functional verification
• Sometimes it’s the little things that bite you.
• Reliability simulation is a largely overlooked area of design verification.

I will cover many of these topics in my March 17th EDN cover story on IC Simulation.

In the meantime, here is my new version of the KISS strategy:

It’s not all about functional verification. RTL is not real.

Know it’s the silicon…