http://vlsi.pro/sva-basics-bind/ 转帖 SVA Basics: Bind System Verilog Assertions Binding SVA module to design can be done using system verilog bind statement. This is semantically equivalent to instantiation of SVA module. The bind directive can be specified in a module, interfa ...
slave sequence, 基本上是作为 responder的。 由于slave sequence 不知道(hard to predict)什么时候需要respond,一般我们都做成无限循环的(lasting-long)的sequence,持续整个simulation,提供response服务。 mentor的解决办法以下两条: • Using a single sequence item • Using a sequence item ...